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| 型號： | AD9910BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 34/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標(biāo)準包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9910
Data Sheet
Rev. D | Page 4 of 64
REVISION HISTORY
5/12—Rev. C to Rev. D
Changes to Table 1............................................................................ 8
Changes to Table 3.......................................................................... 12
Changes to Figure 39...................................................................... 31
Changes to Synchronization of Multiple Devices Section ........ 45
Changes to Table 18........................................................................ 55
Changes to Table 20........................................................................ 58
Changes to Table 26........................................................................ 60
8/10—Rev. B to Rev. C
Changes to XTAL_SEL Input Parameter in Table 1..................... 8
Changes to Table 2............................................................................ 9
Changes to Transmit Enable (TxENABLE) Section .................. 21
12/08—Rev. A to Rev. B
Changes to Figure 2.......................................................................... 5
Changes to I/O_UPDATE Pulse Width Parameter and
Minimum Profile Toggle Period Parameter in Table 1................ 7
Added XTAL_SEL Input Parameter in Table 1............................. 8
Changes to Table 3.......................................................................... 11
Changes to Figure 20...................................................................... 16
Changes to Figure 22...................................................................... 17
Changes to Figure 23...................................................................... 18
Changes to Figure 24...................................................................... 19
Changes to Figure 25...................................................................... 20
Changes to REF_CLK/REF_CLK Overview Section................. 24
Changes to Crystal Driven REF_CLK/REF_CLK Section........ 25
Changes to PLL Lock Indication Section and Output Shift
Keying (OSK) Section .................................................................... 27
Changes to DRG Slope Control Section and Normal Ramp
Generation Section......................................................................... 30
Changes to Drover Pin Section..................................................... 32
Changes to Figure 43...................................................................... 35
Changes to Figure 45 and Internal Profile Control Continuous
Waveform Timing Diagram Section............................................ 38
Changes to Figure 47...................................................................... 40
Changes to Figure 48...................................................................... 41
Deleted I/O_UPDATE Pin Section.............................................. 41
Changes to Profiles Section........................................................... 42
Added I/O_UPDATE, SYNC_CLK, and System Clock
Relationships Section..................................................................... 42
Added Figure 49; Renumbered Sequentially .............................. 42
Changes to Synchronization of Multiple Devices Section ........ 44
Changes to DVDD (1.8V) (Pin 17, Pin 23, Pin 30, Pin 47,
Pin 57, and Pin 64) Section and AVDD (1.8V) (Pin 89 and
Pin 92) Section................................................................................ 47
Changes to Control Interface—Serial I/O Section .................... 48
Changes to Table 17 ....................................................................... 50
Changes to Table 19 ....................................................................... 57
Changes to Table 20 and Table 21 ................................................ 58
2/08—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to REFCLK Multiplier Specification in Table 1.............5
Changes to Minimum Setup Time to SYNC_CLK.......................6
Changes to I/O Update/Profile[2:0] Timing Characteristics ......6
Changes to TxENABLE/Data Setup Time (to PDCLK) and
TxENABLE/Data Hold Time (to PDCLK) ....................................6
Changes to Miscellaneous Timing Characteristics.......................6
Changes to Table 3.......................................................................... 10
Changes to Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,
and Figure 14................................................................................... 12
Changes to Figure 30 and Table 7................................................. 24
Changes to Automatic I/O Update Section................................. 41
Added Table 16, Renumbered Sequentially ................................ 41
Changes to Figure 49 to Figure 53................................................ 43
Added Power Supply Partitioning Section.................................. 46
Changes to General Serial I/O Operation Section..................... 47
Changes to Table 17 ....................................................................... 49
Changes to Table 19 ....................................................................... 56
Changes to Table 20 ....................................................................... 57
Added Table 32 ............................................................................... 60
5/07—Revision 0: Initial Version
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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