參數(shù)資料
型號(hào)： AD9910BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 38/64頁(yè)
文件大小： 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
Data Sheet
AD9910
Rev. D | Page 43 of 64
AUTOMATIC I/O UPDATE
The AD9910 offers an option whereby the I/O update function
is asserted automatically rather than relying on an external signal
supplied by the user. This feature is enabled by setting the internal
I/O update active bit in Control Function Register 2 (CFR2).
When this feature is active, the I/O_UPDATE pin becomes an
output pin. It generates an active high pulse each time an inter-
nal I/O update occurs. The pulse width is determine by the I/O
update rate control bits (CFR2[15:14]). Table 16 approximates the
pulse width setting.
Table 16. Pulse Width Setting
I/O Update Rate Control Bits
(CFR2[15:14])
I/O Update Pulse Width
00
12 SYSCLKs
01
24 SYSCLKs
10
48 SYSCLKs
11
96 SYSCLKs
This I/O update strobe can be used to notify an external
controller that the device has generated an I/O update
internally.
The repetition rate of the internal I/O update is programmed
via the serial I/O port. There are two parameters that control
the repetition rate. The first consists of the two I/O update rate
control bits in CFR2. The second is the 32-bit word in the I/O
update rate register that sets the range of an internal counter.
The I/O update rate control bits establish a divide-by-1, -2, -4,
or -8 of a clock signal that runs at fSYSCLK. The output of the
divider clocks the aforementioned 32-bit internal counter. The
repetition rate of the I/O update is given by
B
f
A
SYSCLK
UPDATE
O
I
2
_
/
2
+
=
where:
A is the value of the 2-bit word comprising the I/O update rate
control bits.
B is the value of the 32-bit word stored in the I/O update rate
register.
The default value of A is 0, and the value of B is 0xFFFF. If B is
programmed to 0x0003 or less, the I/O_UPDATE pin no longer
pulses but assumes a static Logic 1 state.
POWER-DOWN CONTROL
The AD9910 offers the ability to independently power down
four specific sections of the device. Power-down functionality
applies to the following:
Digital core
DAC
Auxiliary DAC
Input REFCLK clock circuitry
A power-down of the digital core disables the ability to update
the serial I/O port. However, the digital power-down bit can
still be cleared via the serial port to prevent the possibility of a
nonrecoverable state.
Software power-down is controlled via four independent power-
down bits in Control Function Register 1 (CFR1). Software
control requires that the EXT_PWR_DWN pin be forced to a
Logic 0 state. In this case, setting the desired power-down bits
(via the serial I/O port) powers down the associated functional
block, whereas clearing the bits restores the function.
Alternatively, all four functions can be simultaneously powered
down via external hardware control through the EXT_PWR_DWN
pin. When this pin is forced to Logic 1, all four circuit blocks are
powered down regardless of the state of the power-down bits;
that is, the independent power-down bits in CFR1 are ignored
and overridden when EXT_PWR_DWN is Logic 1.
Based on the state of the external power-down control bit, the
EXT_PWR_DWN pin produces either a full power-down or a
fast recovery power-down. The fast recovery power-down mode
maintains power to the DAC bias circuitry and the PLL, VCO,
and input clock circuitry. Although the fast recovery power-
down does not conserve as much power as the full power-down,
it allows the device to awaken very quickly from the power-
down state.
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