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參數(shù)資料
| 型號： | AD9910BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 41/64頁 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標準包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9910
Data Sheet
Rev. D | Page 46 of 64
across all the devices. If the SYNC_INx signal is edge aligned at all
devices, and all devices have the same sync receiver delay and
sync state preset value, then they all have matching clock states
(that is, they are synchronized). This concept is shown in
Figure 53, in which three AD9910 devices are synchronized,
with one device operating as a master timing unit and the
others as slave units.
The master device must have its SYNC_INx pins included as part
of the synchronization distribution and delay equalization mecha-
nism in order for it to be synchronized with the slave units.
The synchronization mechanism begins with the clock distribu-
tion and delay equalization block, which is used to ensure that
all devices receive an edge-aligned REFCLK signal. However,
even though the REFCLK signal is edge aligned among all devices,
this alone does not guarantee that the clock state of each internal
clock generator is coordinated with the others. This is the role
of the synchronization and delay equalization block. This block
accepts the SYNC_OUTx signal generated by the master device
and redistributes it to the SYNC_INx input of the slave units (as
well as feeding it back to the master). The goal of the redistributed
SYNC_OUT x signal from the master device is to deliver an
edge-aligned SYNC_INx signal to all of the sync receivers.
Assuming that all devices share the same REFCLK edge (due to
the clock distribution and delay equalization block), and all
devices share the same SYNC_INx edge (due to the synchroni-
zation and delay equalization block), then all devices should
generate an internal sync pulse in unison (assuming that they
all have the same sync receiver delay value). With the further
stipulation that all devices have the same sync state preset value,
then the synchronized sync pulses cause all of the devices to
assume the same predefined clock state simultaneously; that is,
the internal clocks of all devices become fully synchronized.
The synchronization mechanism depends on the reliable gen-
eration of a sync pulse by the edge detection block in the sync
receiver. Generation of a valid sync pulse, however, requires
proper sampling of the rising edge of the delayed SYNC_INx signal
with the rising edge of the local SYSCLK. If the edge timing of
these signals fails to meet the setup or hold time requirements
of the internal latches in the edge detection circuitry, then the
proper generation of the sync pulse is in jeopardy. The setup
and hold validation block (see Figure 54) gives the user a means
to validate that proper edge timing exists between the two signals.
The setup and hold validation block can be disabled via the
sync timing validation disable bit in Control Function Register 2.
The validation block makes use of a user-specified time window
(programmable in increments of ~75 ps via the 4-bit sync
validation delay word in the multichip sync register). The setup
validation and hold validation circuits use latches identical to
those in the rising edge detector and strobe generator. The
programmable time window is used to skew the timing between
the rising edges of the local SYSCLK signal and the rising edges
of the delayed SYNC_INx signal. If either the hold or setup
validation circuits fail to detect a valid edge sample, the condition
is indicated externally via the SYNC_SMP_ERR pin (active high).
The user must choose a sync validation delay value that is a
reasonable fraction of the SYSCLK period. For example, if the
SYSCLK frequency is 1 GHz (1 ns period), then a reasonable
value is 4 (300 ps). Choosing too large a value can cause the
SYNC_SMP_ERR pin to generate false error signals. Choosing
too small a value may cause instability.
SYNC
PULSE
SYSCLK
DELAY
CHE
CK
L
O
G
IC
4
SYNC VALIDATION
DELAY
4
SYNC_SMP_ERR
SYNC RECEIVER
12
SYNC TIMING VALIDATION DISABLE
SETUP
VALIDATION
HOLD
VALIDATION
D Q
12
SETUP AND HOLD VALIDATION
TO
CLOCK
GENERATION
LOGIC
FROM
SYNC
RECEIVER
DELAY
LOGIC
D Q
RISING EDGE
DETECTOR
AND STROBE
GENERATOR
06479-
054
Figure 54. Sync Timing Validation Block
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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