參數(shù)資料
型號(hào)： AD9910BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/64頁(yè)
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
AD9910
Data Sheet
Rev. D | Page 28 of 64
Automatic OSK
In automatic mode, the OSK function automatically generates a
linear amplitude vs. time profile (or amplitude ramp). The ampli-
tude ramp is controlled via three parameters: the maximum
amplitude scale factor, the amplitude step size, and the time
interval between steps. The amplitude ramp parameters reside
in the 32-bit ASF register and are programmed via the serial
I/O port. The time interval between amplitude steps is set via
the 16-bit amplitude ramp rate portion of the ASF register
(Bits[31:16]). The maximum amplitude scale factor is set via the
14-bit amplitude scale factor in the ASF register (Bits[15:2]). The
amplitude step size is set via the 2-bit amplitude step size
portion of the ASF register (Bits[1:0]). Additionally, the
direction of the ramp (positive or negative slope) is controlled
by the external OSK pin.
The step interval is controlled by a 16-bit programmable timer
that is clocked at a rate of fSYSCLK. The period of the timer sets
the time interval between amplitude steps. The step time interval
(Δt) is given by
SYSCLK
f
M
t
4
Δ =
where M is the 16-bit number stored in the amplitude ramp rate
(ARR) portion of the ASF register. For example, if fSYSCLK =
750 MHz and M = 23218 (0x5AB2), then Δt ≈ 123.8293 μs.
The output of the OSK function is a 14-bit unsigned data bus
that controls the amplitude parameter of the DDS (as long as
the OSK enable bit is set). When the OSK pin is set, the OSK
output value starts at 0 (zero) and increments by the pro-
grammed amplitude step size until it reaches the programmed
maximum amplitude value. When the OSK pin is cleared, the
OSK output starts at its present value and decrements by the
programmed amplitude step size until it reaches 0 (zero).
The OSK output does not necessarily attain the maximum
amplitude value if the OSK pin is switched to Logic 0 before the
maximum value is reached. Nor does the OSK output necessarily
reach a value of 0 if the OSK pin is switched to Logic 1 before
the 0 value is reached.
The OSK output is initialized to 0 (zero) at power-up and reset
whenever the OSK enable bit or the select auto OSK bit is cleared.
The amplitude step size of the OSK output is set by the amplitude
step size bits in the ASF register according to Table 10. The step
size refers to the LSB weight of the 14-bit OSK output. Regardless
of the programmed step size, the OSK output does not exceed
the maximum amplitude value programmed into the ASF
register.
Table 10. OSK Amplitude Step Size
Amplitude Step Size Bits (ASF[1:0])
Amplitude Step Size
00
1
01
2
10
4
11
8
As mentioned previously, a 16-bit programmable timer controls
the step interval. Normally, this timer is loaded with the pro-
grammed timing value whenever the timer expires, initiating a
new timing cycle. However, there are three events that can cause
reloading of the timer to have its timing value reloaded prior to
the timer expiring. One such event occurs when the select auto
OSK bit transitions from cleared to set, followed by an I/O update.
A second such event is a change of state in the OSK pin. The
third is dependent on the status of the load ARR @ I/O update
bit. If this bit is cleared, then no action occurs; otherwise, when
the I/O_UPDATE pin is asserted (or a profile change occurs),
the timer is reset to its initial starting point.
DIGITAL RAMP GENERATOR (DRG)
DRG Overview
To sweep phase, frequency, or amplitude from a defined start
point to a defined endpoint, a completely digital, digital ramp
generator is included in the AD9910. The DRG makes use of
nine control register bits, three external pins, two 64-bit
registers, and one 32-bit register (see Figure 37).
DIGITAL RAMP LIMIT REGISTER
DRCT
L
DDS CLOCK
DRHO
L
D
DRO
V
E
R
DIGITAL RAMP RATE REGISTER
DIGITAL RAMP STEP REGISTER
06479-
018
TO DDS
SIGNAL
CONTROL
PARAMETER
DIGITAL RAMP ENABLE
DROVER PIN ACTIVE
LOAD LRR AT I/O_UPDATE
CLEAR DIGITAL
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
RAMP ACCUMULATOR
64
DIGITAL RAMP DESTINATION
2
DIGITAL RAMP NO-DWELL
2
32
DIGITAL
RAMP
GENERATOR
62
61
63
Figure 37. Digital Ramp Block Diagram
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