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| 型號： | AD9910BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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Data Sheet
AD9910
Rev. D | Page 29 of 64
The primary control for the DRG is the digital ramp enable bit.
When disabled, the other DRG input controls are ignored and the
internal clocks are shut down to conserve power.
The output of the DRG is a 32-bit unsigned data bus that can be
routed to any one of the three DDS signal control parameters, as
controlled by the two digital ramp destination bits in Control
Function Register 2 according to Table 11. The 32-bit output
bus is MSB-aligned with the 32-bit frequency parameter, the
16-bit phase parameter, or the 14-bit amplitude parameter, as
defined by the destination bits. When the destination is phase
or amplitude, the unused LSBs are ignored.
Table 11. Digital Ramp Destination
Digital Ramp
Destination Bits
(CFR2[21:20])
DDS Signal
Control
Parameter
Bits Assigned to
DDS Parameter
00
Frequency
31:0
01
Phase
31:16
Amplitude
31:18
1 x = Don’t care.
The ramp characteristics of the DRG are fully programmable. This
includes the upper and lower ramp limits, and independent control
of the step size and step rate for both the positive and negative slope
characteristics of the ramp. A detailed block diagram of the DRG is
shown in Figure 38.
The direction of the ramping function is controlled by the
DRCTL pin. A Logic 0 on this pin causes the DRG to ramp
with a negative slope, whereas a Logic 1 causes the DRG to
ramp with a positive slope.
The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is set to Logic 1, the DRG is stalled at its last
state; otherwise, the DRG operates normally.
The DDS signal control parameters that are not the destination of
the DRG are taken from the active profile.
DDS CLOCK
D
Q
R
LOWER
LIMIT
0
1
DECREMENT STEP SIZE
PRESET
Q
DRCTL
LOAD
CLEAR DIGITAL RAMP ACCUMULATOR
AUTOCLEAR DIGITAL RAMP ACC
.
NO DWELL
LIMIT CONTROL
DIGITAL RAMP ACCUMULATOR
INCREMENT STEP SIZE
32
0
1
NEGATIVE SLOPE RATE
POSITIVE SLOPE RATE
16
32
16
62
DRHOLD 63
32
LOAD
CONTROL
LOGIC
LOAD LRR AT I/O_UPDATE
DIGITAL
RAMP
TIMER
ACCUMULATOR
RESET
CONTROL
LOGIC
NO-DWELL
CONTROL
2
32
TO DDS
SIGNAL
CONTROL
PARAMETER
UPPER
LIMIT
32
06479-
019
Figure 38. Digital Ramp Generator Detail
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| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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