參數(shù)資料
型號： AD9910BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 30/64頁
文件大小： 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
AD9910
Data Sheet
Rev. D | Page 36 of 64
RAM Ramp-Up Internal Profile Control Mode
Table 14. RAM Internal Profile Control Modes
Internal Profile Control Bits (CFR1[20:17])
Waveform Type
Internal Profile Control Description
0000
Internal profile control disabled.
0001
Burst
Execute Profile 0, then Profile 1, then halt.
0010
Burst
Execute Profile 0 to Profile 2, then halt.
0011
Burst
Execute Profile 0 to Profile 3, then halt.
0100
Burst
Execute Profile 0 to Profile 4, then halt.
0101
Burst
Execute Profile 0 to Profile 5, then halt.
0110
Burst
Execute Profile 0 to Profile 6, then halt.
0111
Burst
Execute Profile 0 to Profile 7, then halt.
1000
Continuous
Execute Profile 0, then Profile 1, continuously.
1001
Continuous
Execute Profile 0 to Profile 2, continuously.
1010
Continuous
Execute Profile 0 to Profile 3, continuously.
1011
Continuous
Execute Profile 0 to Profile 4, continuously.
1100
Continuous
Execute Profile 0 to Profile 5, continuously.
1101
Continuous
Execute Profile 0 to Profile 6, continuously.
1110
Continuous
Execute Profile 0 to Profile 7, continuously.
1111
Invalid.
Ramp up internal profile control mode is invoked via the four
internal profile control bits (rather than through the RAM
profile mode control bits in the RAM profile registers).
If any of the internal profile control bits is set, then the RAM
profile mode control bits of the RAM profile registers are
ignored. The no-dwell high bit is ignored in this mode. The
internal profile control mode is identical to ramp-up mode
except that profile switching is done automatically and
internally; the state of the PROFILE[2:0] pins is ignored.
Profiles cycle according to Table 14.
There are two types of waveform generation types available
under internal profile control: burst waveforms and continuous
waveforms. With both types, the state machine begins with the
waveform specified by the waveform start address, waveform
end address, and address ramp rate in Profile 0. After reaching
the waveform end address of Profile 0, the state machine automati-
cally advances to the next profile and initiates the specified
waveform as defined by the new profile parameters. After the
state machine reaches the waveform end address of the new
profile, it advances to the next profile. This action continues
until the state machine reaches the waveform end address of
the last profile, as governed by the internal profile control bits in
Control Function Register 1 (CFR1) per Table 14.
At this point, the next course of action depends on whether the
waveform type is burst or continuous. For burst waveforms, the
state machine halts operation after reaching the waveform end
address of the final profile. For continuous waveforms, the state
machine automatically jumps to Profile 0 and continues the
automatic waveform generation by sequentially advancing
through the profiles. This process continues indefinitely until
the internal profile control bits are reprogrammed and an I/O
update is asserted.
A burst waveform timing diagram is exemplified in Figure 44.
The diagram assumes that the internal profile control bits in
Register CFR1 are programmed as 0010, the start address in
RAM Profile 1 is greater than the end address in RAM Profile 0,
and that the start address in RAM Profile 2 is greater than the
end address in RAM Profile 1. However, the block of RAM
associated with each profile can be chosen arbitrarily based on
the waveform start address and waveform end address for each
profile. Furthermore, the example shows how different Δt
values associated with each profile can be used.
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