參數(shù)資料
型號： AD9910BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/64頁
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
AD9910
Data Sheet
Rev. D | Page 12 of 64
Pin No.
Mnemonic
I/O1
Description
59
I/O_UPDATE
I/O
Input/Output Update. Digital input (active high). A high on this pin transfers the contents
of the I/O buffers to the corresponding internal registers.
60
OSK
I
Output Shift Keying. Digital input (active high). When the OSK features are placed in either
manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles
the multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero, a high sweeps the amplitude
up to the amplitude scale factor.
61
DROVER
O
Digital Ramp Over. Digital output (active high). This pin switches to Logic 1 whenever the
digital ramp generator reaches its programmed upper or lower limit.
62
DRCTL
I
Digital Ramp Control. Digital input (active high). This pin controls the slope polarity of the
digital ramp generator. See the Digital Ramp Generator (DRG) section for more details. If
not using the digital ramp generator, connect this pin to Logic 0.
63
DRHOLD
I
Digital Ramp Hold. Digital input (active high). This pin stalls the digital ramp generator in
its present state. See the Digital Ramp Generator (DRG) section for more details. If not
using a digital ramp generator, connect this pin to Logic 0.
67
SDIO
I/O
Serial Data Input/Output. Digital input/output (active high). This pin can be either unidirec-
tional or bidirectional (default), depending on the configuration settings. In bidirectional serial
port mode, this pin acts as the serial data input and output. In unidirectional mode, it is an
input only.
68
SDO
O
Serial Data Output. Digital output (active high). This pin is only active in unidirectional
serial data mode. In this mode, it functions as the output. In bidirectional mode, this pin is
not operational and should be left floating.
69
SCLK
I
Serial Data Clock. Digital clock (rising edge on write, falling edge on read). This pin provides
the serial data clock for the control data path. Write operations to the AD9910 use the
rising edge. Readback operations from the AD9910 use the falling edge.
70
CS
I
Chip Select. Digital input (active low). This pin allows the AD9910 to operate on a common
serial bus for the control data path. Bringing this pin low enables the AD9910 to detect
serial clock rising/falling edges. Bringing this pin high causes the AD9910 to ignore input
on the serial data pins.
71
I/O_RESET
I
Input/Output Reset. Digital input (active high). This pin can be used when a serial I/O
communication cycle fails (see the I/O_RESET—Input/Output Reset section for details).
When not used, connect this pin to ground.
80
IOUT
O
Open-Drain DAC Complementary Output Source. Analog output (current mode). Connect
through a 50 resistor to AGND.
81
IOUT
O
Open-Drain DAC Output Source. Analog output (current mode). Connect through a 50
resistor to AGND.
84
DAC_RSET
O
Analog Reference Pin. This pin programs the DAC output full-scale reference current.
Attach a 10 k resistor to AGND.
90
REF_CLK
I
Reference Clock Input. Analog input. When the internal oscillator is engaged, this pin can
be driven by either an external oscillator or connected to a crystal. See the REF_CLK/ Overview
section for more details.
91
REF_CLK
I
Reference Clock Input. Analog input. See the REF_CLK/ Overview section for more details.
94
REFCLK_OUT
O
Crystal Output. Analog output. See the REF_CLK/ Overview section for more details.
95
XTAL_SEL
I
Crystal Select (1.8 V Logic). Analog input (active high). Driving the XTAL_SEL pin high,
the AVDD (1.8V) pin enables the internal oscillator to be used with a crystal resonator.
If unused, connect it to AGND.
EPAD
Exposed Paddle
(EPAD)
The EPAD should be soldered to ground.
1 I = input, O = output.
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