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參數(shù)資料
| 型號： | AD9910BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 57/64頁 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9910
Data Sheet
Rev. D | Page 60 of 64
Multichip Sync Register—Address 0x0A
Four bytes are assigned to this register.
Table 26. Multichip Sync Register
Bit(s)
Mnemonic
Description
31:28
Sync validation delay
This 4-bit number sets the timing skew (in ~75ps increments) between SYSCLK and the
delayed SYNC_INx signal for the sync validation block in the sync receiver. Default is 0000b.
27
Sync receiver enable
0 = synchronization clock receiver disabled (default).
1 = synchronization clock receiver enabled.
26
Sync generator enable
0 = synchronization clock generator disabled (default).
1 = synchronization clock generator enabled.
25
Sync generator polarity
0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).
1 = synchronization clock generator coincident with the falling edge of SYSCLK.
24
Open
23:18
Sync state preset value
This 6-bit number is the state that the internal clock generator assumes when it receives a
sync pulse. Default is 000000b.
17:16
Open
15:11
Output sync generator
delay
This 5-bit number sets the output delay (in ~75 ps increments) of the sync generator.
Default is 00000b.
10:8
Open
7:3
Input sync receiver delay
This 5-bit number sets the input delay (in ~75 ps increments) of the sync receiver. Default is
00000b.
2:0
Open
Digital Ramp Limit Register—Address 0x0B
Eight bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.
Table 27. Bit Descriptions for Digital Ramp Limit Register
Bit(s)
Mnemonic
Description
63:32
Digital ramp upper limit
32-bit digital ramp upper limit value.
31:0
Digital ramp lower limit
32-bit digital ramp lower limit value.
Digital Ramp Step Size Register—Address 0x0C
Eight bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.
Table 28. Bit Descriptions for Digital Ramp Step Size Register
Bit(s)
Mnemonic
Description
63:32
Digital ramp decrement
step size
32-bit digital ramp decrement step size value.
31:0
Digital ramp increment
step size
32-bit digital ramp increment step size value.
Digital Ramp Rate Register—Address 0x0D
Four bytes are assigned to this register. This register is only effective if CFR2[19] = 1. See the Digital Ramp Generator (DRG) section for
details.
Table 29. Bit Descriptions for Digital Ramp Rate Register
Bit(s)
Mnemonic
Description
31:16
Digital ramp negative slope
rate
16-bit digital ramp negative slope value that defines the time interval between decrement
values.
15:0
Digital ramp positive slope
rate
16-bit digital ramp positive slope value that defines the time interval between increment
values.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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