參數(shù)資料
型號(hào)： AD9910BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/64頁(yè)
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
Data Sheet
AD9910
Rev. D | Page 11 of 64
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O1
Description
1, 20, 72, 86, 87,
93, 97 to 100
NC
Not Connected. Allow device pins to float.
2
PLL_LOOP_FILTER
I
PLL Loop Filter Compensation Pin. See the External PLL Loop Filter Components section for
details.
3, 6, 89, 92
AVDD (1.8V)
I
Analog Core VDD, 1.8 V Analog Supplies.
74 to 77, 83
AVDD (3.3V)
I
Analog DAC VDD, 3.3 V Analog Supplies.
17, 23, 30, 47,
57, 64
DVDD (1.8V)
I
Digital Core VDD, 1.8 V Digital Supplies.
11, 15, 21, 28, 45,
56, 66
DVDD_I/O (3.3V)
I
Digital Input/Output VDD, 3.3 V Digital Supplies.
4, 5, 73, 78, 79, 82,
85, 88, 96
AGND
I
Analog Ground.
13, 16, 22, 29, 46,
51, 58, 65
DGND
I
Digital Ground.
7
SYNC_IN+
I
Synchronization Signal (LVDS), Digital Input (Rising Edge Active). The synchronization
signal from the external master to synchronize internal subclocks. See the Synchronization
of Multiple Devices section for details.
8
SYNC_IN
I
Synchronization Signal (LVDS), Digital Input. The synchronization signal from the external
master to synchronize internal subclocks. See the Synchronization of Multiple Devices
section for details.
9
SYNC_OUT+
O
Synchronization Signal (LVDS), Digital Output (Rising Edge Active). The synchronization
signal from the internal device subclocks to synchronize external slave devices. See the
10
SYNC_OUT
O
Synchronization Signal (LVDS), Digital Output. The synchronization signal from the internal
device subclocks to synchronize external slave devices. See the Synchronization of Multiple
Devices section for details.
12
SYNC_SMP_ERR
O
Synchronization Sample Error, Digital Output (Active High). Sync sample error: a high on
this pin indicates that the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN.
14
MASTER_RESET
I
Master Reset, Digital Input (Active High). Master reset: clears all memory elements and sets
registers to default values.
18
EXT_PWR_DWN
I
External Power-Down, Digital Input (Active High). A high level on this pin initiates the
currently programmed power-down mode. See the Power-Down Control section for
further details. If unused, connect to ground.
19
PLL_LOCK
O
Clock Multiplier PLL Lock, Digital Output (Active High). A high on this pin indicates that the
Clock Multiplier PLL has acquired lock to the reference clock input.
24
RAM_SWP_OVR
O
RAM Sweep Over, Digital Output (Active High). A high on this pin indicates that the RAM
sweep profile has completed.
25 to 27, 31 to 39,
42 to 44, 48
D[15:0]
I
Parallel Input Bus (Active High).
49, 50
F[1:0]
I
Modulation Format Pins. Digital input to determine the modulation format.
40
PDCLK
O
Parallel Data Clock. This is the digital output (clock). The parallel data clock provides a
timing signal for aligning data at the parallel inputs.
41
TxENABLE
I
Transmit Enable. Digital input (active high). In burst mode communications, a high on this
pin indicates new data for transmission. In continuous mode, this pin remains high.
52 to 54
PROFILE[2:0]
I
Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight
phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the
current contents of all I/O buffers to the corresponding registers. State changes should be
set up on the SYNC_CLK pin.
55
SYNC_CLK
O
Output Clock Divided-By-Four. A digital output (clock). Many of the digital inputs on the
chip, such as I/O_UPDATE and PROFILE[2:0], need to be set up on the rising edge of this signal.
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