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參數(shù)資料
| 型號(hào)： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 9/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
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9
ZR38650
Hosts
A host microprocessor is not required for the ZR38650’s opera-
tion. A custom program, in either the internal ROM or an external
ROM with the standard internal ROM, is sufficient. Control of the
operation is then through the GPIO (General Purpose Input/Out-
put) ports.
However, the greatest flexibility is available if a host is used. The
least costly in external hardware is a serial host interface. The
four-wire SPI (Small Peripheral Interface) or two-wire Z2C
signals (see Table 6) connect directly to most low-cost micro-
controllers. There is no speed penalty with a host serial interface
and it leaves the parallel interface free for use with external
memories.
The ZR38650’s parallel interface can be used for a byte-wide
connection to a microprocessor host along with byte-wide I/O
with the standard command support. The full 32-bits of the
parallel interface can be used for an I/O connection if called in
the developer’s software. Note that the parallel interface can not
be used concurrently for the host and I/O while it is being used
for external data or program memory.
Data Input/Output
The primary data input is the single-wire digital audio interface
receiver. This conforms fully to S/PDIF, IEC-958, AES/EBU and
EIAJ CP-340 consumer standards. All standard sampling rates
are supported for raw or packetized bitstreams as well as the
data driven master operation using the DREQ signal on the
GPIO0 port. Serial port A or the byte-wide parallel interface may
alternately be used for the channel bitstream as master or slave.
The parallel interface also provides data driven master opera-
tion, but it can not be used concurrently with external memory in
the system.
Up to six channels of bit-serial ADC data can be input as master
or slave in a wide variety of industry formats when required by
SiliconSoftwarefunctions.
Up to eight channels of bit-serial DAC data can be output as
master or slave in the same variety of industry formats including
I
2
S and EIAJ with word, frame and frameless synchronization.
Ports B,C and D are used by standard 6-channel functions with
Port G in addition for 8-channel SiliconSoftwarefunctions. Oth-
erwise Port G serves as a S/PDIF master transmitter.
External Memory
The 20 address and 32 data lines of the parallel port allow a wide
choice of external memory for program and data storage if
needed for SiliconSoftware functions or for future flexibility.
Variable wait-states are supported for slower, lower cost memo-
ries. Not used concurrently with parallel host or I/O interfaces.
Hardware - Digital Audio Processor
The ZR38650 is composed of the interfaces, memories and
system clocks that surround the ZR38001 DSP core shown in
Figure 5. The individual signals of each of the interfaces and
power supply connection are summarized in Table 6.
The figure illustrates the sharing of the serial output port G with
the S/PDIF transmitter and the multiple functions of the parallel
port for the external host, I/O and memories. Note from Table 6
how some of the otherwise unused 32-bit memory data lines are
utilized for additional control when the parallel byte-wide inter-
face is employed for the external host and I/O.
Using standard functions, three of the six GPIO signals are ded-
icated as a MUTE input, an I/O data request output, DREQ, and
an I/O error output, ERROR.
Figure 4. Software Memory Configurations
ZR38650
Host
Processor
RAM Image
SiliconSoftware
3-D Audio
Program/
Data
ROM
Program/
Data
RAM
Program ROM or
Flash EPROM
I/O
DVD
Home THX
Music Modes
Bass Management
OR
Custom, Etc.
RAM Image
SiliconSoftware
3-D Audio
DVD
Home THX
Music Modes
Bass Management
Custom, Etc.
RAM Image
SiliconSoftware
3-D Audio
DVD
Home THX
Music Modes
Bass Management
Custom, Etc.
Standard ROM
Set-Up
System
Operation
Standard Functions
Pri. Decode & Test
Custom ROM
Standard and Custom
Functions
Set-Up
System
Operation
Decode & Test
Program/Data
RAM or ROM
32
Byte-Wide
Program ROM
8
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