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參數(shù)資料
| 型號(hào)： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 11/66頁 |
| 文件大小： | 441K |
| 代理商： | ZR38650 |
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11
ZR38650
Table 6: ZR38650 Signal Description Summary
Name
Number
Type
[1]
Description
Parallel Port (56)
A[19:0]
D[31:15]
D14/RDY
D13/ C/D
D12/ERR
D[11:4]/PP[7:0]
D[3:0]
CS
RD
WR
P/M
20
17
1
1
1
8
4
1
1
1
1
O
I/O
Address bus of parallel port
Data bus of parallel port when selected for external memory (P/M = 0)
Data bus (P/M = 0) or Ready output signal of parallel port when selected for parallel I/O (P/M = 1)
Data bus (P/M = 0) or Command/Data select input of parallel port when selected for parallel I/O (P/M = 1)
Data bus (P/M = 0) or Error input signal of parallel port when selected for parallel I/O (P/M = 1)
Data bus of parallel port when selected for external memory (P/M = 0) or Parallel Port I/O (P/M = 1)
Data bus of parallel port when selected for external memory (P/M = 0)
Chip Select output for external memory or Chip Select input for parallel I/O
Read enable output for external memory or Read enable input for parallel I/O
Write enable output for external memory or Write enable input for parallel I/O
Parallel I/O or Memory select for parallel port. Determined at time of RESET.
Serial Ports (13)
S/PDIF Receiver input port
Serial Data inputs. Ports A, E and F.
Word Select or Frame Synchronization for input ports. An output when a master, an input when a slave.
Serial Clock for input ports. An output when a master, an input when a slave.
Serial left and right Data output. Port B. Also, at RESET defines SPI/Z2C for host serial interface.
Serial left and right surround Data output. Port C. Also, at RESET defines Z2CADR[0] of Z2C address.
Serial center and sub-woofer Data output. Port D. Also, at RESET defines Z2CADR[1] of Z2C address.
Serial Data output. Port G or S/PDIF Transmitter port. Also, at RESET defines the SCKP value.
Word Select or Frame Synchronization for output ports. An output when a master, an input when a slave.
Serial Clock for output ports. An output when a master, an input when a slave.
Serial master Clock output or master clock Input for output ports
General Purpose Ports (6)
Mute input signal or can be programmed as General Purpose Input/Output 5
Can be programmed as General Purpose Input/Output 4, 3 and 2
Error output signal or can be programmed as General Purpose Input/Output 1
Data Request output signal or can be programmed as General Purpose Input/Output 0
Serial Host Interface (4)
Host Serial interface data Input. Also, at RESET defines Z2CADR[5] of Z2C address.
SPI host Serial interface data Output or Serial Data for Z2C
SPI host Serial interface Clock input or Slave Clock input for Z2C
SPI host serial interface Slave Select input. Also, at RESET defines Z2CADR[4] of Z2C address.
ICE Interface (4)
ICE Test interface Data Input, Clock input and Mode Select
ICE Test interface Data Output
System Interface (8)
External Interrupt request input
Reset input to start operation in known state
Determines location on Memory Map of reset and interrupt block
External system clock Input or connection to external crystal, at frequency f
XTI
Output connection to external crystal
Clock Output from the ZR38650 at frequency f
DSP
/2
Bypass internal DSP core PLL to use external system clock input on XTI
External Filter Capacitor connection for PLL. A value of 47nF is recommended.
Power (43)
+3.3 volt power supply
+3.3 volt power supply, Analog for PLL
Power supply Ground
Power supply Ground, Analog for PLL
Total (144) = Active (134) + No Connection (10)
I/O or O
I/O or I
I/O or I
I/O
I/O
I/O
I/O
I/O
I
SPFRX
SDA, SDE, SDF
WSA/FSA
SCKA
SDB
SDC
SDD
SDG/SPFTX
WSB/FSB
SCKB
SCKIN
1
3
1
1
1
1
1
1
1
1
1
I
I
I/O
I/O
O
O
O
O
I/O
I/O
I/O
MUTE/GPIO5
GPIO[4:2]
ERROR/GPIO1
DREQ/GPIO0
1
3
1
1
I or I/O
I/O
O or I/O
O or I/O
SI
SO/SDA
SCK/SCL
SS
1
1
1
1
I
I/O/T
I
I
TDI, TCK, TMS
TDO
3
1
I
O/T
INT
RESET
MMAP
XTI
XTO
CLKOUT
BYPASS
FLTCAP
1
1
1
1
1
1
1
1
I
I
I
I
O
O
I
I
VDD
VDDA
GND
GNDA
16
1
25
1
Power
Power
Power
Power
1. O = Output, I = Input, T = Tri-state in normal use. May be different at Reset time as shown in Table 23 on page 42.
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