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參數(shù)資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 36/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
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36
ZR38650
Input/Output Ports
Connections to external memory and peripherals are made
through the input/output ports. There is a single 32-bit parallel
data port, eight serial data ports and six single-bit general
purpose I/O ports (GPIO). These last can be configured by the
user as outputs or inputs.
Parallel Port
The ZR38650 parallel port works in two separate modes which
are selected by the pin P/M at RESET. It can work as a data
parallel port which is used to load data, instructions and
programs to the chip and read status and other information from
the chip, or it may work as an external memory interface. The
external memory interface consists of the 20-bit address bus
A[19:0], the 32-bit bi-directional data bus D[31:0], and the control
signals CS, RD and WR. The data parallel port interface consists
of the 8-bit bi-directional data bus PP[7:0], and the control
signals CS, RD, WR, ERR, C/D, RDY. The RDY, C/D, and ERR
signals are D[14:12] and PP[7:0] are D[11:4] also.
When controlling the external memory interface (P/M = 0), CS is
asserted low whenever there is an access to external memory.
RD is asserted during an external read cycle, and can be used
as an output enable for memory. WR is asserted during an
external write cycle and can be used as a write enable for
memory.
The ZR38650 can generate wait-states for use with slow
external memory using the WAIT field of the CFG command. In
access cycles with wait-states, the timing relationship of the
transitions of the memory interface signals remain the same as
in a zero-wait cycle, but all are stretched by the specified number
of instruction clock periods (1, 3 or 7).
During an instruction cycle in which there is no external data
access, the RD and WR signals are not active. However, the
address bus continues to be driven with the internal instruction
fetch address.
When the parallel I/O interface is selected (P/M = 1), an internal
FIFO is used to enable the host to write data in long bursts. The
RDY output signal indicate when the FIFO is ready to receive
more data (RDY = 1) or when the FIFO is almost full and not
ready to accept data (RDY = 0). The ERR signal is an input to
indicate for each data byte received if there is an error in the
data. The C/D input signal distinguishes between input data and
instructions or status which use the HREGIN/HREGOUT regis-
ters. When C/D = 1 transfers are a host command or reply status
and therefore are written to the HREGIN register or read from
the HREGOUT register. When C/D = 0 then all data from the
host is written to the internal FIFO. CS, RD and WR are always
inputs when P/M = 1. When RESET is asserted, the address and
data buses and control signals CS, RD and WR are all set to a
high-impedance state.
Serial DAC and ADC Ports
The serial ports are flexible on the ZR38650 to serve a wide
variety of applications and peripheral devices. The three ADC
inputs and four DAC outputs may be variously grouped to share
two sets of common control signals, each being a master or a
slave. Other selections are word or frame synchronization,
frame size and either 16, 18, 20 or 24-bit word transfers. A
master clock output which can be generated internally and two
group programmable rate clocks. The I
2
S format, the frame-less
time-division-multiplex (TDM) format and the LSB justified frame
of the EIAJ format are all supported.
Ports A, E, F are always ADC data inputs, while B, C, D are
always DAC data outputs. Port G can be a DAC data output or
the S/PDIF transmitter output. The ports may be configured in
two groups with shared clocking: all inputs and all outputs, or as
two groups with one of the inputs in the outputs group. This
selection is made by the AB bit in the Mode register. The B group
is unique in that when operating as a source to DACs, its clock
outputs can also be derived from an externally supplied master
clock input (SCKIN).
Transfers are on the positive- or negative-going edge of the bit-
rate clocks (SCKA and SCKB) with the most significant bit being
shifted first into or out of the double buffered shift registers. Word
boundaries are signaled by a single-bit-duration frame signal
(FSA and FSB) for each word or an alternating word signal
(WSA and WSB) indicating left or right channel, even or odd
word. The signal type is selected independently for each group
as is the word length of 16, 18, 20 or 24 bits and the frame size
of 16 to 256 bits per frame. The Word Select bits in the Status
register reflect when the left or right channel is being transferred
for each group. The WS/FS signals maybe advanced by one or
more bit intervals for the non-I
2
S format. Completed frame trans-
fers for each group are indicated to the processor by a vectored
interrupt when individually enabled. An exception is for TDM
where there is an interrupt for each word within a frame.
Each group can be a source or a slave as selected in the auxil-
iary Serial Port Mode register. When a source, the clock rates
are independently programmable sub-multiples of the internally
generated master clock. The B group clocks can come from the
external master clock input (SCKIN) as well. If this input is not
used the pin may be selected as an output for the internally gen-
erated master clock.
S/PDIF Serial Ports
The SPFRX signal is the single-wire input to the S/PDIF digital
audio receiver. In use, the Audio PLL locks on the incoming
SPFRX bitstream to determine the audio master clock SCKIN
and to recover the digital input data.
The serial output Port G is the single-wire S/PDIF digital audio
transmitter output when not used as a DAC data output. Its
SDG/SPFTX signal is used to output S/PDIF encoded data for
decoding in other peripheral devices.
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