參數(shù)資料
型號(hào)： ZR38650
廠商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁(yè)數(shù)： 34/66頁(yè)
文件大小： 441K
代理商： ZR38650
34
ZR38650
for the output serial ports, and the serial port shift register
pointers are reset. The modulus registers and the loop end reg-
isters are cleared. The program counter is set to Hex E0000
before unconditionally jumping to the beginning of the Reset and
Interrupt block (shown in Table 17) to start executing the reset
service routine. The complete service routine may be read from
an external bootstrap device and in turn, executed.
Assertion of RESET does not affect the stack pointer, loop start
register, loop and repeat count registers, address and index reg-
isters, internal RAM and the data registers.
The 15 hardware interrupts and the software Interrupt, have their
corresponding vector addresses and the priority shown in Table
17. The priority reflects only the order of servicing when more
than one request is pending, and does not determine whether or
not a currently executing interrupt service routine will itself be
interrupted. All interrupts are collectively disabled with the IE bit
and individually enabled with their own mask bits in the auxiliary
Interrupt Mask Register (IMR). Before an interrupt service
routine is executed, the processor clears the IE bit to disable
further interrupts and then pushes the return address and Status
register contents on to the stack.
RePeaT and LOOP Instructions
The RePeaT instruction allows the single instruction that follows
it to be repeated with no instruction overhead beyond the initial
single RePeaT instruction. The Repeat Count (RC) register in
the Program Sequence Unit allows up to 2
20
repeated opera-
tions. Likewise, the LOOP instruction allows zero overhead for
repeating multiple instruction sequences. The Loop Count (LC),
the Loop Start (LS) and the Loop End (LE) registers implement
this instruction. Loops may be nested up to four deep with these
registers automatically being pushed on their individual stacks.
The RC, LC, LS and LE can be a source or destination for
general register data transfers, with each transfer in or out of the
LE register being the appropriate push or pop operation respec-
tively for their stacks.
Subroutines and Stack Operations
An operational stack is maintained in data memory to service
context switches caused by changes in control flow. Interrupts
as well as the PUSH, POP and Jump SubRoutine instruction
macros use the stack. The Stack Pointer (SP) in the Address
Generation Unit determines the stack location, usually in the
internal Data or Program/Data RAM for highest speed.
Instruction Unit
Pipeline
Each instruction is fetched from program memory (either internal
RAM or ROM), decoded in the Instruction register and finally
executed. This three stage instruction pipeline takes a minimum
of three instruction cycles, but is generally transparent to the
user. The delayed branch instructions, however clearly exhibit
this pipeline’s delay. The pipeline is extended, in effect,
whenever there is a requirement for multiple simultaneous
accesses to a particular memory resource that cannot be
resolved in a single cycle. This occurs, for example, when an
instruction fetch and a dual data move all require access to the
internal Program/Data RAM or ROM.
Instruction Set
Each of the instructions of the ZR38650 is a single word in length
and except for program flow control instructions, all generally
execute in a single cycle unless multiple external memory
accesses are required. Much of the power of the processor lies
in the parallel operations that go on within one instruction.
Instructions are named for the dominant operation that exe-
cutes, usually an Arithmetic Unit operation or a Program
Sequence Unit operation. The instruction set names are sum-
marized in Table 18 by the functional unit. Also listed are the
instruction macros which the assembler generates from the
basic instructions.
Table 17: Reset and Interrupt Block Memory Map
Interrupt
Number
Priority
Offset
Interrupt Type
Mask
0
1
(highest)
0x00
Reset Service Routine
no
1
2
0x04
ICE Interrupt Service Routine
no
2
3
0x08
Breakpoint Interrupt Service Routine
no
3
10
0x0C
HREG Interrupt Service Routine
yes
4
5
0x10
INT External Interrupt Service Routine
yes
5
6
0x14
Serial Port Group A Service Routine
yes
6
0x18
Reserved
7
8
0x1C
Serial Port Group B Service Routine
yes
8
0x20
Reserved
9
9
0x24
Serial Host Interrupt Service Routine
yes
10
0x28
Reserved
11
7
0x2C
Audio Receiver Error Interrupt Service
Routine
yes
12
4
0x30
Data FIFO Interrupt Service Routine
yes
13
11
0x34
Timer Service Routine
yes
14
0x38
Reserved
15
16
0x3C
Jump to Software Interrupt Service Routine
no
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