參數(shù)資料
型號： ZR38650
廠商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁數(shù)： 17/66頁
文件大?。?/td> 441K
代理商： ZR38650
17
ZR38650
For example, if f
XTI
= 24.576 MHz and f
AUDIO
is 256x a sample
rate of 48 kHz, then AUDM = 1 and AUDD = 2. For the fastest
processor operation if f
XTI
= 24.576 MHz, then f
DSP
= 99.84 MHz
if DSPM = 65 and DSPD = 16.
See the section OPERATION WITH COMMANDS on page 24
for a more complete description of these settings.
PLL Configuration
PLLCFG
The PLLCFG command defines the PLL programmable config-
uration. It returns the current status of the PLL lock (PLLR).
PLLCFG must be given before a CFG command. The next serial
host command must be delayed by at least 2000 DSP instruction
cycles (40 microseconds at 50 MHz) following a change of F1-
F3, AS, or DS fields.
Set Configuration
CFG
The CFG setup command determines the input, output and
external memory configurations for the ZR38650.
AUDM
Audio PLL Multiplier:
13-bit number
AUDD
Audio PLL Divider:
13-bit number
DSPM
DSP PLL Multiplier:
8-bit number
DSPD
DSP PLL Divider:
6-bit number
SR
Sampling Rate
of output: 0 = 48 kHz, 1 = 44.1 kHz, 2 = 32 kHz,
3 = 96 kHz.
F1
Determines input clock source for audio PLL: 0 = Internal oscil-
lator or XTI input, 1 = S/PDIF mode using SPFRX.
F2
Determines audio clock f
AUDIO
source: 0 = Audio PLL, 1 =
Internal oscillator or XTI input at f
XTI
.
Determines master clock output frequency f
SCKIN
: 0 = Audio
clock frequency f
AUDIO
, 1 = One-half audio clock frequency
(f
AUDIO
/2).
Audio PLL Set
: 0 = No action, 1 = Resets Audio PLL.
F3
AS
DS
DSP PLL Set
: 0 = No action, 1 = Resets DSP core PLL
Parameter 1
0
1
2
3
4
5
6
7
1
0
0
1
1
0
0
1
Command
DS
AS
F2
F1
F3
SR
0
1
2
3
4
5
6
7
0
1
0
0
0
0
0
1
WAIT
0
0
0
0
WFB
WFA
0
0
MA
MB
CB
DVD
0
PES
FRA
FRB
CPA
CPB
OSP
ISP
0
0
EPE
MPE
0
DRQ
PDI
OUTW
INW
SPO
AVS
SEN
SPAS
SPBS
FMA
FMB
0
Parameter 4
Parameter 5
Parameter 6
Parameter 7
Parameter 8
Parameter 3
Parameter 1
Parameter 2
Command
WFA
Word/Frame
synchronization for inputs: 0 = Frame,
1 = Word.
WFB
Word/Frame
synchronization for outputs: 0 = Frame,
1 = Word.
WAIT
Wait-state
cycles for external memory: 0 = None, 1 = One,
2 = Three, 3 = Seven.
PES
PES
packetized input: 0 = Disabled, 1 = Enabled.
DVD
DVD
mode: 0 = Disabled, 1 = Enabled.
CB
Clock
source for outputs: 0 = SCKIN input pin, 1 = Internal,
using the SPBS scaler with the Audio PLL or system clock.
MB
Master
mode for output clocking: 0 = Slave, 1 = Master.
MA
Master
mode for input clocking: 0 = Slave, 1 = Master.
CPB
Serial
Clock B Polarity
: 0 = Negative, 1 = Positive.
CPA
Serial
Clock A Polarity
: 0 = Negative, 1 = Positive.
FRB
Frame
size (bits) for outputs: 0 = 16, 1 = 32, 2 = 64,
3 = 128, 4 = 192, 5 = 256, 6 = 193, 7 = 24. Normal
value = 1.
FRA
Frame
size (bits) for input: 0 = 16, 1 = 32, 2 = 64, 3 = 128,
4 = 192, 5 = 256, 6 = 193, 7 = 24. Normal value = 1.
DRQ
Data Request
output pin DREQ (GPIO0): 0 = Disabled,
1 = Enabled.
MPE
Mute Pin Enable
: 0 = Mute determined by host command,
1 = Mute determined by MUTE (GPIO5) input pin.
EPE
Error Pin Enable
for ERROR output pin (GPIO1): 0 = Dis-
abled, 1 = Enabled.
ISP
Input Word Select Polarity
: 0 = Left is WS low, 1 = Left is
WS high.
OSP
Output Word Select Polarity
: 0 = Left is WS low, 1 = Left
is WS high.
SEN
S/PDIF
input selection: 0 = Input from SRA register,
1 = Input from S/PDIF receiver SPRXDAT register.
AVS
Audio/Video Synchronization
: 0 = Disabled, 1 = Enabled.
SPO
S/PDIF Output
: 0 = Disabled, 1 = Enabled.
INW
Input Word
: 0 = 20 bits, 1 = 18 bits, 2 = 16 bits, 3 = 24 bits.
OUTW
Output Word
: 0 = 20 bits, 1 = 18 bits, 2 = 16 bits, 3 = 24
bits.
PDI
Parallel Data Interface
for data input stream: 0 = Serial, 1
= Parallel.
SPAS
Group A internal clock divider.
SPBS
Group B internal clock divider.
FMB
Format of serial ports group B: 0-5 = Delay bits, 6 = TDM
mode, 7 = Right justified mode (maximum delay is 64).
FMA
Format of serial ports group A: 0-5 = Delay bits, 6 = TDM
mode, 7 = Right justified mode (maximum delay is 64).
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