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參數(shù)資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 27/66頁 |
| 文件大小： | 441K |
| 代理商： | ZR38650 |
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27
ZR38650
Digital Audio Receiver
The digital audio receiver function of the ZR38650 is fully com-
pliant with the IEC-958, S/PDIF, AES/EBU and EIAJ CP-340
consumer mode interface standards. It will lock on to the
incoming bitstream and extract the clock and data information.
The data is supplied to the processor for decoding and the clock
is multiplied to yield a 256x or 384x sample rate, as required by
the DACs. This master clock signal is available on the SCKIN pin
as an output.
For correct operation of the S/PDIF receiver the following initial-
ization steps are required:
The AUDD variable in the PLLTAB command should be set
to approximately 128 x f
XTI
, where f
XTI
is the clock input fre-
quency expressed in MHz (i.e. if f
XTI
= 12.288 MHz, then
AUDD equals the integer portion of 12.288 x 128 = 1572).
AUDM should be set to 4 or 6, for 256x or 384x sample rate
audio clock output, respectively.
The F1 field in the PLLCFG command should be set to 1.
The SEN field in the CFG command should be set to 1.
Other representative values for AUDM/AUDD, F3 and SPBS
when using the S/PDIF receiver are given in Table 14 for various
sample rates and master clock rates. They are for the common
choice of a system clock frequency (f
XTI
) of 24.576 MHz
.
Digital Audio Transmitter
The digital audio transmitter of the ZR38650 is fully compatible
with IEC-958, S/PDIF, AES/EBU and EAIJ CP-340 consumer
mode standards. This function enables the transmission of
digital audio bitstreams to an external decoder for processing in
all modes of operation, i.e. AC-3, MPEG or PCM. The transmit-
ter is enabled by setting the SPO bit in the CFG command. The
Channel Status information required by IEC-958 should be
supplied to the ZR38650 through the SPDIFCS command See
the section S/PDIF Channel Status SPDIFCS on page 18. It is
important to set the Channel Status bits for an external decoder
to operate correctly. When the S/PDIF output is enabled, the
fourth serial port SDG is disabled. Note that the output frame
size must be 32 bits (FRB = 1) when using the S/PDIF output.
General Purpose Ports
There are six single-bit general purpose ports GPIO[5:0]
normally configured as inputs at reset. GPIO5 is normally used
as the MUTE input and GPIO0 as the DREQ output. GPIO1 is
normally the ERROR output signal. GPIO[5:0] may be config-
ured as user defined outputs by setting the GPIOC field in the
SETIO command. Inputs pins, the ones that are defined as
inputs from GPIO[5:0], are sampled and read from the GPIO
register by the host with the SETIO command. At the same time
it can set the state of the pins that are configured as output pins.
Decoder Operation
A typical decoder function selection command sequence would
be:
AC3, UNMUTE...MUTE...PROL, UNMUTE...
where AC-3 is selected first, then followed by a switch to
ProLogic at a later time. If the DRQ bit in command CFG is set,
the command sequence must include a PLAY:
AC3, PLAY, UNMUTE...MUTE, STOP...MPEG, PLAY,
UNMUTE....
Table 14: Example SPBS, AUDM/AUDD and F3 Settings using the S/PDIF Receiver and a 24.576 MHz System
Clock f
XTI
f
s
Master
Clock
Master Clock
f
SCKIN
12.288 MHz
F3
Audio Clock (f
AUDIO
)
12.288 MHz
AUDM/AUDD
SPBS
SCKB Output (64 f
s
)
3.072 MHz
48 kHz
256 f
s
384 f
s
256 f
s
128 f
s
0
4/3416
2
44.1 kHz
16.9344 MHz
0
16.9344 MHz
6/3416
3
2.8224 MHz
32 kHz
8.192 MHz
0
8.192 MHz
4/3416
2
2.048 MHz
96 kHz
12.288 MHz
1
24.576 MHz
4/3416
2
6.144 Mhz
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