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參數資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數字音頻處理器 |
| 文件頁數： | 32/66頁 |
| 文件大小： | 441K |
| 代理商： | ZR38650 |
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32
ZR38650
register file from memory in parallel with a three operand multi-
plier and ALU operation, including storing the result, every
instruction cycle.
In addition to the basic two’s-complement arithmetic and logical
operations, the 48-bit ALU also can find minimums and maxi-
mums, normalize, determine exponents for block floating-point,
support multiple precisions and perform division primitives. A
further refinement is a butterfly primitive that computes both a
product sum and difference using an auxiliary adder. This
fetching of four operands, doing a multiply, addition and subtrac-
tion and storing two results facilitates a very fast 4-cycle radix-2
FFT butterfly. ALU results set appropriate Status register bits in
the System Interface, which has sticky bits for multiple precision
and array computations. A large class of immediate data logical
and arithmetic instructions free register space and reduce
instruction count in the bit operations so common in communica-
tions coding applications.
The multiplier provides both signed and unsigned operations
with an optional one-bit left shift on the output determined by the
MS bit in the Mode register. This shift for fractional number align-
ment preserves the maximum 42 bits of shifted products. The
48-bit barrel shifter does both logical and arithmetic shifts; the
SD bit in the Mode register allows a positive shift operator to be
interpreted as either a left or a right direction shift. A third Data
Shifter provides arithmetic shifts, rounding and limiting when
transferring data from the register file onto the Data Bus. The
shifting range of 1 bit to the right through to 2 bits to the left is
determined by the DS bits in the Mode register.
Two of the eight registers of the register file (D0 & D1) are 48
bits, the remaining six are 20 bits and align as shown in
Figure 13. In general all arithmetic unit operations are for implicit
20-bit operands with data being overflowed, limited, rounded or
truncated accordingly for registers D2-D7. However when D0 or
D1 are the source or destination, then the operations are such
as to preserve the full 48-bit precision results in these registers.
Likewise, transfers in and out of D0 & D1 with the data buses are
extended or reduced based on their being 48-bit operands.
These two registers usually serve as the high precision accumu-
lators which are central to most signal processing algorithms.
Any of the three fields can be explicitly addressed if the implicit
operands are not the desired ones.
Address Generation Unit
Data operated on by the Arithmetic Unit is read from and
restored to the Data Register File. Register file locations are
directly addressed by register fields within the operate field of
the instructions. For data transfers with the larger internal and
external memories and registers, direct addressing can also be
used, but indirect addressing by the Address Generation Unit is
often faster and more program memory efficient. The Address
Generator can sequentially produce two 20-bit addresses for the
two bus transfers possible per cycle and post-modify the same
two addresses in the same instruction cycle.
The indirect addresses generated can be linearly incremented
or decremented, indexed, bit-reverse indexed or circular with an
arbitrary modulus M. This is done in the Address Generation
Unit by the Address ALU (AALU) and the Address Register File
which is organized as in Figure 14. The next address is
produced in a postmodify operation using the appropriate sum of
the address register Ax with index register Ix and a compare with
modulus register Mx. The five addressing modes in their assem-
bler notation are:
Note there is no indexing or circular addressing for the stack
pointer SP. For M = Hex FFFFF the corresponding A register is
incremented in a bit-reverse manner for doing the radix-2 FFT.
For an N-point FFT the incrementing index register must be
loaded with N/2.
The Address Register File is accessible on the Data Bus and
can be used for general purpose registers. Further, they can be
loaded with immediate data from the Program Data Bus.
Memory
Internal
There are three internal on-chip memories, a 10k x 20-bit RAM,
a 2k x 32-bit Program RAM and a 20k x 32-bit mask-program-
D1
D0
High
Middle
Low
Figure 13. Data Register File
47 D1H 40 39
47 D0H 40 39
20
20
D1M
D0M
19
19
0
0
D1L
D0L
19
0
D2
19
0
D3
19
0
D4
19
0
D5
19
0
D6
19
0
D7
(ax)
At the address in address register Ax with no postmodify
operation
(ax)+
With a postincrement by one
(ax)-
With a postdecrement by one
(ax)+i
With a postincrement by the value in index register Ix
(ax)-i
With a postdecrement by the value in index register Ix
Address
Figure 14. Data Register File
19
0
A0
Index
19
0
I0
Modulus
19
0
M0
19
0
A1
19
0
I1
19
0
M1
19
0
A2
19
0
I2
19
0
M2
19
0
A3
19
0
I3
19
0
M3
19
0
A4
19
0
I4
19
0
M4
19
0
A5
19
0
I5
19
0
M5
19
0
A6
19
0
I6
19
0
M6
19
0
A7
19
0
I7
19
0
M7
Stack Pointer
Program Counter
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