參數(shù)資料
型號(hào)： ZR38650
廠商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁(yè)數(shù)： 41/66頁(yè)
文件大?。?/td> 441K
代理商： ZR38650
41
ZR38650
SCKP bit in the SPIMODE register is set at Reset if the
SDG/SPFTX pin is tied to a pull-up resistor, or cleared if the pin
is pulled down.
In Z2C operation, byte transfers are half-duplex with the
ZR38650 either a slave-receiver or slave-transmitter. Figure 16
shows a normal read operation by the host master. Normal oper-
ation is in the alternating single-byte transmit/receive protocol,
but the transmit-only protocol can be used to speed program
downloading. The 400 kbit/second fast mode transfer rate is
supported as well as standard mode of 100 kbit/second.
In Circuit Emulation Interface
The ZR38650’s In Circuit Emulation (ICE) capability for both
hardware and software debugging is provided through four test
pins (TDI, TDO, TCK, TMS) using a standard JTAG interface.
This interface is serviced by routines in the on-chip Pro-
gram/Data ROM and the highest priority interrupt. This provides
register and memory read and set commands for hardware
debugging. Three breakpoint address-detection registers and
two count registers with interrupt additionally provide for real-
time program debugging capability in the ICE.
Reset and Initialization
The processor can be reset only by asserting the RESET signal
input pin externally. On the initial power-up it must be asserted
for a minimum of 160 clock cycles with proper supply voltage
operating conditions. Operation starts 16 cycles after the rising
edge. After power-up, any reset must be asserted for at least 16
clock cycles but less than 128 clock cycles if there is no need to
reset the PLLs. If the user wishes to reset the PLLs the reset
signal must be active for at least 160 clock cycles. Operation
starts 16 cycles after the rising edge at the selected reset service
routine location in memory. The processor will not, however,
accept a serial host command and return a response until 200
instruction cycles have elapsed. In order for the decoder to
operate correctly, the following sequence of commands should
be supplied: PLLTAB, PLLCFG, CFG, AC-3 (if AC-3 mode is
required) UNMUTE.
The states of pins after reset that are tri-state or can be either
input or output are given in Table 23.
External Interrupts
The external interrupt input signal INT is edge-sensitive and
must remain asserted for two clock cycles to set the internal INT
flag. This flag is cleared as the interrupt service routine starts so
that any new interrupt condition must allow INT to go high and
then low again for another interrupt to be generated.
Oscillator and Clock Inputs
The XTI and XTO signals jointly supply the oscillator clock f
XTI
either as an input from a TTL system clock or as the crystal con-
nection to enable the internal oscillator. The maximum
frequency f
XTI
is 40 MHz and the minimum is 4 MHz. An internal
phase-locked-loop (PLL) generates from this a DSP core clock
f
DSP
. This internal DSP clock can be in the range of 4-100 MHz.
(For low f
DSP
frequencies, care should be taken because the
SPI data rate is slowed down proportionally). After RESET but
before PLL lock, f
DSP
= f
XTI
.
The external clock is applied to XTI, while the external crystal
connection is as shown in Figure 17. A parallel-resonant funda-
mental-mode crystal should be used with two 20-pF capacitors.
SDA
ADDR6
ADDR4 ADDR3 ADDR2 ADDR1
R
ACK
ADDR5
MSB
ADDR0
ACK
LSB
1
3
4
5
6
7
8
2
1
2
3
4
6
5
9
8
9
7
SCL
ZR38650 is Slave Receiver (SR)
ST
SR
SR
Stop
Start
ZR38650 is Slave Transmitter (ST)
Figure 16. A Z2C Host Interface Read Operation by a Master Host
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