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參數(shù)資料
| 型號(hào)： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 40/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
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40
ZR38650
One of the more generally important Auxiliary Registers is
described next in detail.
Serial Ports Mode Register
The Serial Ports Mode register is an auxiliary source or destina-
tion register containing fields that determine the serial ports
operation and configuration. The fields are defined below.
Timer
The ZR38650 timer is an 18-bit programmable counter auxiliary
register. Once loaded, it counts down at the instruction cycle rate
of f
CLKOUT
or f
DSP
/2. At a count of one it issues an interrupt and
reloads to continue counting the next interval.
Serial Host Interface
The serial host interface provides a low-cost, low-bandwidth
interface to a host processor for down-loading RAM programs
and basic operating commands. The ZR38650 always operates
as a slave and transfers are internal program interrupt driven.
There are the two industry standard signals and protocols sup-
ported, SPI (Serial Peripheral Interface) and Z2C (Zoran Two
Conductor interface). Transfers are bit-serial with parallel eight-
bit data registers. The standard function ROM can accept
commands or down-load RAM program through the serial host
interface if it does not find an external byte-wide EPROM at
Reset time.
The serial host signals and protocol are determined by SPI/Z2C,
the state of the SDB pin at Reset. SPI/Z2C = 0 for Z2C if SDB is
tied to a pull-down resistor. SPI/Z2C = 1 for SPI if SDB relies on
the internal pull-up resistor or uses an external one. The shared
interface signals are data input (SI), data output or slave data
(SO/SDA), serial clock input (SCK/SCL) and slave select (SS),
where SDA and SCL are for the two-wire Z2C interface.
Four auxiliary registers receive data (SPIRX/SCRX), transmit
data (SPITX/SCTX), govern operation (SPIMODE/SCMODE)
and provide control flags (SPISTAT/SCSTAT) for the interrupt
driven operation with the two protocols. An additional auxiliary
register Z2CADR holds the seven-bit Z2C address determined
at Reset from the SI, SS, SDD and SDC pins for
Z2CADR[5,4,1,0] respectively. Z2CADR[6,3,2] are always zero.
In SPI operation, transfers are full-duplex with a single byte
transmitted to the host for every byte received. The polarity of
the SCK clock is defined by the SCKP bit in the SPIMODE
register which is determined by the state of SDG/SPFTX pin at
Reset. When SCKP = 1 the output data on the SO signal
changes after the falling edge of SCK and the input data on the
SI line is sampled on the rising edge of SCK. When SCKP = 0
the output data on SO line changes after the rising edge of SCK
and input data on the SI line is sampled on the falling edge of
SCK. When SS is not asserted, the SCK line should be at the
high level if SCKP = 1 and at the low level if SCKP = 0. The
19
SPFEN
13
14
15
16
17
18
0
0
0
BW1
AW1
0
MB
CB
8
9
10
11
12
0
1
2
3
4
5
6
7
CPA
FRB
FRA
MA
TB
TA
CPB
SPMODE
SPFEN
S/PDIF Output Enable
. Setting SPFEN enables Port G as the S/PDIF output. Clearing it makes Port G serial I/O.
BW1
B Word
precision. Together with the BW bit in the MODE register defines the precision of group B data words. For [BW,BW1]: 0,0
= 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation.
AW1
A Word
precision. Together with the AW bit in the MODE register defines the precision of group A data words. For [AW,AW1]: 0,0
= 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation.
CB
Clock B
source. Selects the group B clock source. Setting CB selects the Audio PLL and SCKIN is an output. Clearing CB selects
SCKIN as the group B clock.
MB
Master B.
Setting MB makes group B outputs masters with SCKB an output. Clearing MB makes group B slaves with SCKB an input.
MA
Master A.
Setting MA makes group A inputs masters with SCKA an output. Clearing MA makes group A slaves with SCKA an input.
TB
TDM B.
Setting TB selects TDM (Time Division Multiplexing) mode for group B outputs with a frame size determined by the FRB
field. Clearing TB disables the TDM mode.
TA
TDM A.
Setting TA selects TDM (Time Division Multiplexing) mode for group A inputs with a frame size determined by the FRA field.
Clearing TA disables the TDM mode.
CPB
Clock Polarity B
determines the group B serial outputs clock polarity. When CPB is set, data is output with the rising edge of the
clock. When CPB is cleared, data is output with the falling edge of the clock.
CPA
Clock Polarity A
determines the group A serial inputs clock polarity. When CPA is set, data is input on the falling edge of the clock.
When CPA is cleared, data is input on the rising edge of the clock.
FRB
Frame B
size. Determines the frame size of the group B serial output ports in master mode: 0 = 16 bits, 1 = 32 bits, 2 = 64 bits, 3 =
128 bits, 4 = 192 bits, 5 = 256 bits, 6 = 193 bits, 7 = 24 bits.
FRA
Frame A
size. Determines the frame size of the group A serial input ports in master mode: 0 = 16 bits, 1 = 32 bits, 2 = 64 bits, 3 =
128 bits, 4 = 192 bits, 5 = 256 bits, 6 = 193 bits, 7 = 24 bits.
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