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參數(shù)資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 25/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
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ZR38650
Input/Output Configuration
The CFG configuration command (see page 17) and the SETIO
command (see page 19) determine the digital input and output
configuration.
Connections to the data stream input, the output DACs and the
single-bit general purpose registers are made through the
input/output ports. There are seven digital audio input and output
ports (Port A, E and F are inputs and Ports B, C, D and G are
outputs). There are six single-bit general purpose user defined
I/O ports: GPIO[5:0].
Serial Ports
The bit-serial ports serve a variety of peripheral device conven-
tions. Their operation is determined solely by the CFG
configuration command. The input Port Group A (serial inputs A,
E, F) and output Port Group B (serial outputs B, C, D and G)
have separate clocking systems and may be individually
selected with the ZR38650 acting as a master or a slave (Port F
can be activated with the clocking systems of Port Group B). The
system clock (f
XTI
), the audio PLL locked to the system clock or
the S/PDIF receiver can generate a master audio clock f
AUDIO
.
This can be used to generate the two internal input and output
bit-rate clocks when they are masters. See Figure 6.
If input port group A is a master, SCKA is at a frequency
f
A
= f
PSA
/(2
·
SPAS) where f
PSA
is the audio clock f
AUDIO
. In the
case where SPAS equals one, f
A
is equal to f
PSA
. The divider
SPAS is a field in the CFG command. Likewise, when output
port group B is master, SCKB is at a frequency
f
B
= f
PSB
/(2
·
SPBS) where f
PSB
is the internal audio clock f
AUDIO
or an external clock f
SCKIN
received through the SCKIN pin. In
the case where SPBS equals one, f
B
is equal to f
PSB
.The
outputs are unique in that when operating as a master their clock
outputs can also be derived from an externally supplied master
clock input (SCKIN) with the programmable divider rate SPBS.
This selection is made with the CB field in the CFG command.
Some of these choices are summarized in Table 12.
Table 10: Representative Values For DSPM And DSPD In The PLLTAB Command
System Clock
Frequency f
XTI
12.288 MHz
Nominal Processor Core Clock Frequency f
DSP
72 MHz
66 MHz
80 MHz
100 MHz
DSPM/
DSPD
Actual f
DSP
66.35 MHz
DSPD
Actual f
DSP
72 MHz
DSPM/
DSPD
Actual f
DSP
79.9 MHz
DSPM/
DSPD
Actual f
DSP
99.8 MHz
27/5
41/7
13/2
65/8
16.9344 MHz
27/7
65.3 MHz
17/4
72 MHz
14/3
79 MHz
35/6
98.8 MHz
18.432 MHz
18/5
66.35 MHz
27/7
71 MHz
13/3
79.9 MHz
65/12
99.8 MHz
24.576 MHz
35/13
66.17 MHz
47/16
72.2 MHz
39/12
79.9 MHz
65/16
99.8 MHz
27.0 MHz
22/9
66.0 MHz
8/3
72.0 MHz
80/27
80.0 MHz
100/27
100.0 MHz
32.0 MHz
33/16
66.0 MHz
9/4
72.0 MHz
5/2
80.0 MHz
25/8
100.0 MHz
Table 11: Representative And Recommended* Values For AUDM/AUDD In The PLLTAB Command
System Clock Frequency f
XTI
12.288 MHz
Serial Audio Master Clock Frequency f
AUDIO
12.288 MHz
(256 x 48 kHz)
(384 x 32 kHz)
8.192 MHz
(256 x 32 kHz)
11.2896 MHz
(256 x 44.1 kHz)
16.9344 MHz
(384 x 44.1 kHz)
18.432 MHz
(384 x 48 kHz)
3/2*
147/160
1/1*
441/320
3/2*
16.9344 MHz
1280/2646
2/3*
640/882
1/1*
960/882
24.576 MHz
1/3*
1/2*
882/128
3/4*
27.0 MHz
1024/3375
784/1875
512/1125
392/625
256/375
32.0 MHz
32/125
441/1250
48/125*
1323/2500
72/125
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