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參數(shù)資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 42/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
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42
ZR38650
Signal Description Summary
Table 23 summarizes information about all pins on the
ZR38650. During reset all T type pins are tri-state and I/O pins
are inputs. Pin states immediately after reset are shown in the
Reset State column. All unused input pins should be connected
to V
DD
if active low, or GND if active high unless internally pulled
low. Unused tri-state pins should be resistively pulled-up to
VDD. Unused outputs should be left unconnected.
Internal pull-downs are 50 μA maximum current sinks and pull-
ups are 50 μA maximum current sources, both are connected
only when configured as an input. The pull-downs on D[31:15]
and D[3:0] are connected only when P/M = 1.
Table 23: ZR38650 Signal Description Summary
Signal Name
Number
of Pins
Type
[1]
Reset
State
[1]
Internally
Pulled
Description
Parallel Port (56)
A[19:0]
20
O/T
O
-
Address bus of parallel port
D[31:15]
17
I/O/T
I
Down
[2]
-
Data bus of parallel port when selected for external memory (P/M = 0)
D14/RDY
1
I/O/T or O
I or O
Data bus (P/M = 0) or Ready output signal of parallel port when selected for
parallel I/O (P/M = 1)
D13/ C/D
1
I/O/T or I
I
-
Data bus (P/M = 0) or Command/Data select input of parallel port when
selected for parallel I/O (P/M = 1)
D12/ERR
1
I/O/T or I
I
-
Data bus (P/M = 0) or Error input signal of parallel port when selected for
parallel I/O (P/M = 1)
D[11:4]/PP[7:0]
8
I/O/T
I
-
Data bus of parallel port when selected for external memory (P/M = 0) or
Parallel Port I/O (P/M = 1)
D[3:0]
4
I/O/T
I
Down
[2]
Data bus of parallel port when selected for external memory (P/M = 0)
CS
1
I/O/T
O or I
Up
Chip Select output for external memory or Chip Select input for parallel I/O
RD
1
I/O/T
O or I
Up
Read enable output for external memory or Read enable input for parallel I/O
WR
1
I/O/T
O or I
Up
Write enable output for external memory or Write enable input for parallel I/O
P/M
1
I
I
-
Parallel I/O or Memory select for parallel port. Determined at time of RESET.
Serial Ports (13)
SPFRX
1
I
I
-
S/PDIF Receiver input port
SDA
1
I
I
-
Serial Data input. Port A.
SDE
1
I
I
-
Serial Data input. Port E.
SDF
1
I
I
-
Serial Data input. Port F.
WSA/FSA
1
I/O
I
Down
Word Select or Frame Synchronization for input ports. An output when a
master, an input when a slave.
SCKA
1
I/O
I
Down
Serial Clock for input ports. An output when a master, an input when a slave.
SDB
1
O
O
Up
Serial left and right Data output. Port B. Also, at RESET defines SPI/Z2C for
host serial interface.
SDC
1
O
O
Up
Serial left and right surround Data output. Port C. Also, at RESET defines
Z2CADR[0] of Z2C address.
SDD
1
O
O
Up
Serial center and sub-woofer Data output. Port D. Also, at RESET defines
Z2CADR[1] of Z2C address.
SDG/SPFTX
1
O
O
-
Serial Data output. Port G or S/PDIF Transmitter port. Also, at RESET defines
the SCKP value.
WSB/FSB
1
I/O
I
Down
Word Select or Frame Synchronization for output ports. An output when a
master, an input when a slave.
SCKB
1
I/O
I
Down
Serial Clock for output ports. An output when a master, an input when a slave.
SCKIN
1
I/O
I
-
Serial master Clock output or master clock Input for output ports
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