- 您現在的位置：買賣IC網 > PDF目錄373821 > ZR38650 (Electronic Theatre Controls, Inc.) PROGRAMMABLE DIGITAL AUDIO PROCESSOR PDF資料下載
參數資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數字音頻處理器 |
| 文件頁數： | 38/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
38
ZR38650
Mode Register
The Mode register is a source or destination register containing
18 fields that define the basic processor configuration. They tend
to be set once at initialization and not change. The interrupt
enable (IE), the wait-state selection (WAIT), and the register file
data shifter (DS) bits that may change during processing are
also individually addressable as registers. The IE, IM, AM and
BM bits are also accessible in the Interrupt Mask Register (IMR).
The Mode register is defined as shown below.
Status Register
The Status register is a source or destination register containing
fields that reflect the state of the processor following each
instruction cycle. They affect the conditional program control of
the processor. The least significant 8 bits reflect arithmetic and
logical operation results from the ALU, multiplier, barrel shifter or
on transfers that involve scaling or limiting. The other eight
involve word identification on the serial and host ports, status of
the PLLs and configuration of the chip. The Status Register is
defined below.
19
IE
13
14
15
16
17
18
AM
BM
0
0
PM
0
WFA
CRCR
8
9
10
11
12
IM
1
2
3
4
5
6
7
MM
WAIT
MS
DS
SD
WBA
AB
AW
BW
MODE
IE
Interrupt Enable
when set enables all unmasked interrupts. When cleared, disables all interrupts.
IM
INT Mask
when set enables the external interrupt input.
AM
A Mask
when set enables the A Group serial ports interrupt.
BM
B Mask
when set enables the B Group serial ports interrupt.
PM
Program Memory
selection. When set the Reset and Interrupt Block is located in internal RAM.
CRCR
CRC R
eset register flag. A transition from ‘0’ to ‘1’ of this flag resets the CRCC register to zero in the next cycle. Cleared at RESET.
WFA
Word/Frame A
group serial port synchronization mode bit. Word synchronization when set, Frame synchronization when cleared.
WFB
Word/Frame B
group serial port synchronization mode bit. Word synchronization when set, Frame synchronization when cleared.
AB
A/B
groupings of serial ports. When set, A Group is ports A, E and B Group is ports B, C, D, F, G. When cleared, A group is port A, E, F
and B Group is ports B, C, D & G.
AW
A Word
precision. Together with the AW1 bit in the SPMODE register defines the precision of group A data words. For [AW,AW1]: 0,0
= 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation.
BW
B Word
precision. Together with the BW1 bit in the SPMODE register defines the precision of group B data words. For [BW,BW1]: 0,0
= 20 bit operation, 0,1 = 18 bit operation, 1,0 = 16 bit operation, 1,1 = 24 bit operation.
MM
Memory Map
. Together with the MMAP pin and PM bit determine the Reset and Interrupt Block start location. Cleared at RESET.
WAIT
Wait-state
selection for external memory. 0 = No wait-states, 1 = One wait-state, 2 = Three wait-states, 3 = Seven wait-states (a total of
eight instruction cycles for an external memory operation).
MS
Multiplier Shifter.
When set specifies 1-bit left arithmetic shift on multiplier output, when cleared there is no shifting.
DS
Data Shifter
on transfers from the Data Register File to memory. 00 = No shift, 01 = Left shift by one, 10 = Left shift by two, 11 = Right
shift by one.
SD
Shift Direction
on the barrel shifter. When cleared a positive shift code corresponds to a left shift, when set a positive shift code corre-
sponds to a right shift.
19
0
13
14
15
16
17
18
0
0
PLOCKA
P/M
SIE
0
0
PLOCKD
8
9
10
11
12
0
1
2
3
4
5
6
7
SS
SL
SV
V
C
N
Z
HWR
WSA
WSB
Q
STATUS
PLOCKA
Audio PLL Lock Status
. Setting RSTAUD resets the audio PLL. This clears PLOCKA indicating that the audio PLL is not locked. When
the audio PLL is locked on the acquired frequency it sets PLOCKA again. Read only.
P/M
Parallel port/Memory
status. The P/M status flag reflects this pin’s state at RESET indicating whether the parallel port is configured
for parallel I/O or memory. Read only.
SIE
Store Interrupt Enable
status Flag. This flag stores the IE value in the mode register upon entering an interrupt processing sequence,
simultaneously with resetting IE flag. Read only.
PLOCKD
DSP PLL Lock Status
. Setting RSTDSP resets the DSP PLL This clears PLOCKD indicating that the PLL is not locked. When the
DSP PLL is locked on the acquired frequency it sets PLOCKD again. Read only.
HWR
Host Write
indicated the host interrupt is due to a write operation to the Host register. Read only.
相關PDF資料 |
PDF描述 |
|---|---|
| ZR38650TQC | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| ZR38650 | Full-Function, High-Performance Programmable Digital Audio Signal Processor(全功能，高性能可編程數字音頻信號處理器) |
| ZR4040-41 | PRECISION 4.1 VOLT MICROPOWER VOLTAGE REFERENCE |
| ZR404005F25 | Circular Connector; No. of Contacts:26; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:16-26 |
| ZR40401F25 | PRECISION 2.5 VOLT MICROPOWER VOLTAGE REFERENCE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ZR38650TQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| ZR391055 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:Integrated DTV System On a Chip |
| ZR39140 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:INTEGRATED DIGITAL TV PROCESSORS |
| ZR39150 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:INTEGRATED DIGITAL TV PROCESSORS |
| ZR39151 | 制造商:ZORAN 制造商全稱:ZORAN 功能描述:INTEGRATED DIGITAL TV PROCESSORS |
發(fā)布緊急采購，3分鐘左右您將得到回復。