參數(shù)資料
型號(hào)： ZR38650
廠商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁(yè)數(shù)： 45/66頁(yè)
文件大?。?/td> 441K
代理商： ZR38650
45
ZR38650
Serial Host And Serial Data
Figure 18 and Figure 19 show a ZR38650 in typical system con-
figurations with a host controller. At Reset time the internal ROM
bootstrap will check for the byte-wide external ROM. A resistive
pull-up on any one data line D[11-4] assures that an external
ROM will not be found. Not finding that, it will then expect to
receive program commands from the host through the selected
serial connection. Note the optional pull-up on SDB in Figure 18
to select the SPI and the pull-down for the Z2C in Figure 19. The
resistive pull-ups/pull-downs on SI, SS, SDC and SDD in Figure
19 determine the ZR38650’s Z2C address at Reset time.
Host
Microprocessor
SI
20 pF
20 pF
XTAL
4-40 MHz
XTI
XTO
GND
GNDA
FLTCAP
47 nF
0.1μF
47 μF
Tant.
VDDA
VDD
+3.3V
27
Ω
SPFRX
GPIO5
SI
SO/
SDA
SCK/
SCL
SS
SO
SCK
SS
RESET
INT
System
Reset
System
Interrupt
SCKIN
WSB
SCKB
SDB
SDC
SDD
ZR38650
DAC
DAC
DAC
Left
Right
Left Surround
Right Surround
Center
Subwoofer
Data
L/R
DCLK
CLK
Data
L/R
DCLK
CLK
Data
L/R
DCLK
CLK
f
S
64 f
S
256 f
S
RS422
Receiver
MUTE
D11
VDD
Figure 18. ZR38650 Typical Configuration With The SPI Serial Interface To A Host Controller
VDD
SCL
Host
Microprocessor
SDA
20 pF
20 pF
XTAL
4-40 MHz
XTI
XTO
GND
GNDA
FLTCAP
47 nF
0.1μF
47 μF
Tant.
VDDA
VDD
+3.3V
27
Ω
SPFRX
GPIO5
SI
SO/
SDA
SCK/
SCL
SS
RESET
INT
System
Reset
System
Interrupt
SCKIN
WSB
SCKB
SDB
SDC
SDD
ZR38650
DAC
DAC
DAC
Left
Right
Left Surround
Right Surround
Center
Subwoofer
Data
L/R
DCLK
CLK
Data
L/R
DCLK
CLK
Data
L/R
DCLK
CLK
f
S
64 f
S
256 f
S
RS422
Receiver
MUTE
D11
VDD
Figure 19. ZR38650 Typical Configuration With The Z2C Serial Interface To A Host Controller
相關(guān)PDF資料
PDF描述
ZR38650TQC PROGRAMMABLE DIGITAL AUDIO PROCESSOR
ZR38650 Full-Function, High-Performance Programmable Digital Audio Signal Processor(全功能，高性能可編程數(shù)字音頻信號(hào)處理器)
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