參數(shù)資料
型號(hào)： ZR38650
廠商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁(yè)數(shù)： 33/66頁(yè)
文件大?。?/td> 441K
代理商： ZR38650
33
ZR38650
mable ROM. The 20-bit wide RAM is used exclusively as data
memory, it transfers on the Data Bus and is addressed only from
the Data Address Bus. It is always located in lowest memory
address space starting at Hex 00000 up to 027FF. The other
RAM and the ROM are 32-bits wide and can be used for both
data and program memory. They are addressable by both the
Program and Data Address Buses and are sources, and the
RAM a destination, for transfers on both Data and Program Data
Buses. When the Program RAM is written to the most significant
12 bits are loaded at the same time from the Data Bus Extension
(DBX) register. When the Program RAM is read as data the DBX
register is loaded with the most significant 12 bits of data. The
DBX register can also be loaded or read as a general register
with data in the least significant 12 bits.
The ROM is always at locations Hex E0000 to E4FFF in memory
space on both Address Buses. The standard ZR38650 product
has the ROM coded with the digital audio decoder functions and
a bootstrap program for accepting commands from a host or
loading an operating program into RAM from a byte-wide
external ROM. Note that the external ROM data is on D[11-4].
The Program/Data RAM is always at locations Hex D0000 to
D07FF in memory space on both Address Buses. It provides fast
internal memory without the cost of a mask programmed internal
ROM when the ZR38650 is used with an external byte-wide
bootstrap ROM or host microcontroller.
All internal memories have a single port, but consistent with the
buses, all can perform two complete operations per instruction
cycle. The memories can operate in parallel provided buses are
available. Each internal address bus has its own address space,
but since the internal memories do not overlap and external
memories share a common address bus, all memories can be
considered to be in one address space as shown in Figure 15.
External
Program/data memory is extended externally on the Parallel
Port in the address spaces shown in Figure 15. Internal data
buses are multiplexed into a single bus for external memory.
Thus only one external data or instruction transfer can take
place at a time. Also, only a single transfer can be made in each
instruction cycle due to the slower external memories. This
memory cycle-time can be lengthened by inserting wait-states to
allow the use of lower-cost slow memories. The number of wait-
states is determined by the CFG command so that external
memory operations take one, three or seven instruction-cycle-
times. The addresses shown are the internal 20-bit ones.
The optional external bootstrap ROM is 8-bits wide and connect-
ed to D[11-4]. Various widths of memory can be used for
external RAM or ROM as required. The choices are 8, 16 or 32
bits. Data must be left justified on the data bus.
Reset and Interrupt Memory Locations
The reset and interrupt vectors occupy a reserved block of
memory of 64 (Hex 40) locations. As shown in Figure 15 these
can be located at the lowest portion of the on-chip 20k x 32-bit
ROM or 2k x 32-bit RAM, or in external memory. This is selected
by the MMAP pin and the MM and PM bits in the Mode Register
as follows:
Program Sequence Unit
All processor operation is governed by the decoded instruction
in the Instruction Register (IR). The control flow of the processor
is the sequence of instructions that are presented to the IR. The
Program Sequence Unit determines this flow by generating the
program address to fetch instructions from program memory.
This unit in the ZR38650 is a powerful address generator also,
often producing a long sequence of operations with a minimum
of program memory transfers. Examples of this are the RePeaT
and LOOP instructions which allow repeated single and multiple
instructions respectively with no instruction overhead. In
addition to these instructions, major changes in the control flow
are determined by the reset operation, interrupts, branches and
subroutines to which the Program Sequence Unit responds.
Reset and Interrupt Operation
Operation of the processor starts with the system asserting the
RESET pin. When RESET is asserted, the Mode Register is set
to Hex 00038 and the Status register is set to Hex 00000. The
serial port data registers are all cleared, as are the shift registers
Reset & Interrupts Location C
02800
40000
00000
E0000
E0040
E5000
Reset & Interrupts Location A
10k x 20 Internal
Data RAM
External Data
Memory
20k x 32 Internal
Program/Data
ROM
Figure 15. Program/Data Memory Map
Memory
Address
(Hex)
D0000
D0040
D0800
2k x 32 Internal
Program/Data
RAM
Reserved for Decoder Functions
4FFFF
Bootstrap
ROM
64k x 8
D11
D4
D0
D19
D4
D11
Reset & Interrupts Location B
80000
80040
Table 16: Reset and Interrupt Start Locations
MMAP
Pin
MM
Bit
PM
Bit
Reset & Interrupts
Location
Start Address
(Hex)
0
0
0
A - Internal ROM
E0000
0
1
0
B - External Memory
80000
1
X
0
B - External Memory
80000
X
X
1
C - Internal RAM
D0000
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