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參數(shù)資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 10/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
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10
ZR38650
Internal memories are large: the 20-kwords of 32-bit pro-
gram/data ROM is augmented with an addition 2-kwords of
down-loadable RAM. The data only memory is a 10-kword RAM
in the 20-bit data word precision.
The two programmable phase-locked-loops (PLLs), one for the
DSP core (f
DSP
) and one for the audio serial ports (f
AUDIO
) allow
independent selection of these two critical internal clock rates.
This is particularly important when the ZR38650 system oscilla-
tor is not determined by its own external crystal, but rather from
a predetermined system clock frequency. Having two PLLs lets
the DSP core synchronously operate at its maximum 50 MIPS
rate (f
DSP
= 100 MHz) for processing while the serial I/O
operates at the standard sample rates of 32, 44.1, 48 or 96 kHz,
regardless of whether the predetermined system clock frequen-
cy is a common sub-multiple.
The power supply is 3.3 Volts for lower power consumption, yet
all I/O signals are 5.0 Volt tolerant for use in 5.0-Volt systems.
Table 5: System Hardware Configurations and Standard Command Support
Hardware Configuration
Hardware Configuration Description
Standard Command Support
Host
None
Custom program using parallel and/or GPIO interface for control.
None. Requires custom internal or
external program ROM.
Bit-serial Interface
Industry standard four-wire SPI duplex or two-wire Z2C half-
duplex.
Yes.
Parallel Interface
Byte-wide selectable for I/O and Commands. Not possible con-
current with external memory.
Yes.
Data Input
S/PDIF Channel
Standard single-wire receiver.
Yes.
Bit-serial Channel
Serial Port A is a flexible slave or data driven master with DREQ.
Yes.
Parallel Channel
Byte-wide master, slave or data-driven master with DREQ. Not
possible concurrent with external memory.
Yes.
ADC bit-serial
Up to six channels as a flexible master or slave.
No.
Data Output
DAC bit-serial
Up to eight channels on Ports B, C, D and G as flexible master
or slave.
Yes for 6-channel ports B, C and D.
S/PDIF Channel
Standard single-wire transmitter on Port G. Master only.
Yes, Port G.
External
Memory
Program/Data ROM
8-, 16- or 32-bit for loading or 32-bit for execution.
Yes for execution or 8-bit only loading.
Program/Data RAM
32-bit memory for executing large functions or 16 or 32 bits for
large delay or table memory.
Not required for standard functions.
Left/Right
Left/Right Surround
Center/Subwoofer
Xtal
S/PDIF
Input
Data/
Control
A
E
F
Address
Test
Control
General Purpose
I/O Ports
Host
Parallel
Port
Serial
Output
Ports
Serial
Input
Ports
B
C
D
Figure 5. ZR38650 Simplified Block Diagram
4
32
20
Serial Host
SPI or Z2C
Interface
Internal Program/
Data ROM
20k x 32
Internal Program/
Data RAM
2k x 32
Internal
Data RAM
10k x 20
4
Serial Audio
Inputs
S/PDIF
Receiver
Parallel Host
Interface
Input Data
FIFO
8 x 9
S/PDIF
Transmitter
Serial Audio
Outputs
Memory
Interface
ICE
Interface
System
Oscillator &
DSP PLL
Audio PLL
GPIO
ZR38001
DSP Core
S/PDIF or
Left/Right Center
4
f
DSP
f
AUDIO
6
f
AUDIO
G
Timer
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