參數(shù)資料
型號(hào)： ZR38650
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁(yè)數(shù)： 39/66頁(yè)
文件大?。?/td> 441K
代理商： ZR38650
39
ZR38650
DBX Register
The data bus extension register (DBX) is a 12-bit register that
permits full use of the 32-bit internal memories for data. When
reading data from 32-bit wide internal memory to a 20-bit regis-
ter, the least significant 20 bits are loaded into the destination
register. The most significant 12 bits are loaded into the DBX
register. When writing data from a 20-bit register to the 32-bit
internal RAM, the least significant 20 bits are driven by the spec-
ified source register, while the most significant 12 bits are driven
by the DBX register. When the DBX is specified as the destina-
tion or source in a transfer, the least significant 12 bits are read
into or loaded from the DBX.
Auxiliary Registers
In addition to the primary data flow and control flow of instruc-
tions between functional units on the two data buses, there is the
secondary control flow with the general and auxiliary registers
for initialization and maintenance operations. The auxiliary reg-
isters are accessed by register-to-register parallel transfers only.
WSA
Word Select
A bit indicates Left channel data is being input if cleared or Right channel data if set, on the A Group serial ports.
WSB
Word Select B
bit indicates Left channel data is being output if cleared or Right channel data if set, on the B Group serial ports.
Q
Quotient
bit is used with the divide iteration instructions.
SS
Sticky Scaling
bit is set if any data transferred through the Data Shifter has a magnitude of greater than 0.25. A typical use is to indicate
the potential for overflow in the next pass of an FFT. It is cleared by a RESET or by an explicit instruction to clear it.
SL
Sticky Limiting
bit is set whenever limiting takes place in the Arithmetic Unit or during a data transfer through the Data Shifter. It is
cleared by a RESET or by an explicit instruction to clear it.
SV
Sticky Overflow
bit is set whenever the Overflow bit is set except for the compare instructions. It is cleared by a RESET or by an
explicit instruction to clear it.
V
Overflow
bit is set if an overflow results from any operation in the Arithmetic Unit. Overflow is determined if any number can not be
properly represented in its destination register.
C
Carry
bit is set if a carry results from an addition or a borrow results from a subtraction in the ALU, or results from shifts in the barrel
shifter of the Arithmetic Unit.
N
Negative
bit is set if the most significant bit of the destination register is set, otherwise it is cleared.
Z
Zero
bit is set if the entire result of an Arithmetic Unit operation in its destination register is zero.
Table 22: The Auxiliary Registers
Name
HREGOUT
HREGIN
ISR
IRR
BKP1
BKP2
BKP3
BCT1
BCT2
BCR
BSR
IMR
GPIOC
SPMODE
AUDM
SPAS
SPBS
SPITX/SCTX
Bits
8
8
1
20
20
20
20
20
20
4
3
20
6
20
13
12
12
8
Description
Host Register Output
Host Register Input (RO)
ICE host Status Register
ICE host Response Register
Instruction address Breakpoint register 1
Instruction address Breakpoint register 2
Data address Breakpoint register 3
Breakpoint 1 Counter
Breakpoint 2 Counter
Breakpoint Control Register
Breakpoint Status Register
Interrupt Mask Register
General Purpose I/O Control register
Serial Ports Mode register
Audio PLL Multiply register
Serial Ports A group Scaler register
Serial Ports B group Scaler register
Serial host Interface Transmit register,
SPI/Z2C
SPIRX/SCRX
8
Serial host Interface Receive register,
SPI/Z2C (RO)
Serial host Interface Mode register,
SPI/Z2C
Serial host Interface Status register, SPI or
Z2C (RO)
Serial port bit Delay A and B
S/PDIF transmitter auxiliary Audio register
S/PDIF Transmitter Status register (RO)
S/PDIF transmitter Channel Status register
DSP PLL Divide/Multiply register
Audio PLL Divide register
ICE Command Register (RO)
ICE Data Register (RO)
Test Mode data register
S/PDIF Receiver Data register (RO)
S/PDIF Receiver Auxiliary register (RO)
S/PDIF Receiver Channel Status (RO)
S/PDIF Receiver Status register (RO)
S/PDIF Receiver Mode register
Cyclic Redundancy Check Code register
Clock Mode register.
Parallel port Data FIFO register (RO)
Parallel port Data FIFO counter (RO)
Timer register
Z2C Address
SPIMO-
DE/SCMODE
SPISTAT/SC
STAT
SPDEL
SPFAUD
SPFSTT
SPFCHS
DSPDM
AUDD
ICR
IDR
TESTMODE
SPRXDAT
SPRXAUX
SPRXCHS
SPRXSTT
SPRXMODE
CRCC
CLKMODE
DFIFO
DFFCNT
TIMER
Z2CADR
2
7
12
7
1
20
14
13
13
20
12
20
6
20
8
4
16
7
20
20
18
7
Table 22: The Auxiliary Registers (Continued)
Name
Bits
Description
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