參數(shù)資料
型號(hào)： ZR38650
廠商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁(yè)數(shù)： 24/66頁(yè)
文件大?。?/td> 441K
代理商： ZR38650
24
ZR38650
OPERATION WITH COMMANDS
This section describes operation principles when using the
command structure and its configuration choices.
Start-Up
After being reset by the system RESET signal, the ZR38650 will
check for an external program ROM to load. Not finding this it will
start execution from the internal ROM and await commands from
the host. Normal host operation would confirm the ROM version
number and then configure the ZR38650 to match the system
and desired operation. The command configuration sequence
PLLTAB, PLLCFG, CFG is mandatory and must precede any
decoding function selection.
The PLL Configuration
Two phase-locked-loops (PLLs) allow independent selection of
the core processor clock rate (f
DSP
) and the serial digital audio
clock rate (f
AUDIO
) for a variety of system clock frequencies (f
XTI
)
and sources. Figure 6 shows the system oscillator, the two
PLLs, the serial I/O divider chains and the interconnection selec-
tions. These are configured with the PLLTAB, PLLCFG and the
CFG commands.
The DSPM and DSPD fields in the PLLTAB command (see
page 16) determine the core processor clock rate to allow a
choice between processing performance and lower power at
lower clock rates. Table 10 shows some representative values
for common system clock frequencies.
The AUDM and AUDD fields in the PLLTAB command deter-
mine the serial digital audio master clock rate for the I/O dividers.
Table 11 shows some representative and recommended values
for common sample rates and master clock multiples.
÷ DSPD
X
DSPM
MUX
÷ 2
÷ AUDD
X
AUDM
MUX
÷ SPBS
÷ 2
System Crystal
Oscillator
Crystal or
External System
Clock Input
(4-40 MHz)
XTI
XTO
DSP Core Clock
(60-100 MHz)
Audio Clock
CB
f
PSB
f
PSA
= f
AUDIO
SPAS=1
SCKA Input Clock
MB
SPBS=1
f
B
BYPASS
System
Clock Output
(30-50 MHz)
CLKOUT
SPFRX
Master Clock
SCKIN
SCKB
SCKA
Serial Clocks
SCKB Output Clock
Input Word/
Frame Sync.
Output Word/Frame
Sync.
0
1
0
1
0
1
Figure 6. The System Clock Oscillator, The DSP PLL And
The Audio PLL With Serial I/O Divider Chains
System Clock
Oscillator
DSP PLL
Audio PLL
Serial I/O
Dividers
MUX
0
1
MUX
÷ SPAS
÷ 2
0
1
MUX
MUX
1
0
MA
f
A
MUX
1
0
÷ FRB
÷ FRA
MB
WSB/FSB
WSA/FSA
MUX
1
0
MA
MUX
1
0
F1
F2
MUX
MUX
F3
÷ 2
0
0
1
1
f
XTI
f
XTI
f
CLKOUT
f
SPFRX
f
DSP
f
AUDIO
(f
SCKIN
)
(f
B
)
(f
A
)
B Group
A Group
Frame Size
Dividers
Word/Frame
Selects
S/PDIF
Receiver
相關(guān)PDF資料
PDF描述
ZR38650TQC PROGRAMMABLE DIGITAL AUDIO PROCESSOR
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