參數(shù)資料
型號(hào)： ZR38650
廠商： Electronic Theatre Controls, Inc.
英文描述： PROGRAMMABLE DIGITAL AUDIO PROCESSOR
中文描述： 可編程數(shù)字音頻處理器
文件頁(yè)數(shù)： 26/66頁(yè)
文件大小： 441K
代理商： ZR38650
26
ZR38650
Table 13 shows some representative values for both SPBS and
AUDM/AUDD for different output sample frequencies (f
S
) and
master clock multiples of the sample frequency. They are for the
common choice of a system clock frequency of 24.576 MHz.
Serial Port Formats
Many choices are possible for the bit-serial port formats and
word sizes. The five most commonly used formats are summa-
rized in Table 15 along with the selectable word sizes.
Waveforms for each are illustrated in Figures 7-11. Note the
various frame durations indicated. Clocking for both master and
slave operation is shown. The transitions marked are the edges
where data changes when the ZR38650 is a master or where the
data is sampled when it is a slave. Settings for the appropriate
fields in the CFG command are also summarized.
Word select (WS) or frame synchronization (FS) is chosen with
the WFA and WFB fields. The polarity of the WS signal is chosen
with the ISP and OSP fields. Either polarity is acceptable on any
of the word select formats. Through the FMA field the frameless
input operation of Format 3 can be chosen. The input then is
sampled every SCKA and an interrupt generated after 16 bits
has been received. Note that when a master the FS signal
shown is, in fact, generated and if FS is asserted when a slave
it will re-synchronize the data as shown. This format may not be
accepted by some function operating modes.
Table 12: Serial Ports A & B Clocking Summary In The CFG And PLLCFG Commands
Function
Input Port Group A
Output Port Group B
Audio PLL source from S/PDIF or System Clock
F1
Audio Clock source from Audio PLL or System Clock
F2
External master clock input SCKIN pin (f
SCKIN
)
Internal master clock (f
PSB
= f
AUDIO
) and Master external clock output pin
Master or slave clocking mode
None
CB field = 0
None
CB field = 1
MA field
MB field
Internal 12-bit master clock scalers for SCKA and SCKB. LS 8-bit fields.
SPAS field (f
A
= f
PS A
/ [2SPAS])
f
A
= f
PSA
if SPAS=1
CPA = 0
SPBS field (f
B
= f
PSB
/ [2SPBS])
f
B
= f
PSB
if SPBS=1
CPB = 0
Bypass of clock scalers
Data latched/sent out on rising/falling edge of clock
Data latched/sent out on falling/rising edge of clock
CPA = 1
CPB = 1
Table 13: Example SPBS And AUDM/AUDD Settings With A 24.576 MHz System Clock f
XTI
f
s
f
AUDIO
256 f
s
384 f
s
512 f
s
256 f
s
f
AUDIO
(SCKIN Output)
12.288 MHz
AUDM/AUDD
SPBS
SCKB Output (64 f
s
)
3.07 MHz
48 kHz
1/2
2
48 kHz
18.432 MHz
3/4
3
48 kHz
24.576 MHz
1/1
4
96 kHz
24.576 MHz
1/1
2
6.144 MHz
相關(guān)PDF資料
PDF描述
ZR38650TQC PROGRAMMABLE DIGITAL AUDIO PROCESSOR
ZR38650 Full-Function, High-Performance Programmable Digital Audio Signal Processor(全功能，高性能可編程數(shù)字音頻信號(hào)處理器)
ZR4040-41 PRECISION 4.1 VOLT MICROPOWER VOLTAGE REFERENCE
ZR404005F25 Circular Connector; No. of Contacts:26; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:16-26
ZR40401F25 PRECISION 2.5 VOLT MICROPOWER VOLTAGE REFERENCE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZR38650TQC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PROGRAMMABLE DIGITAL AUDIO PROCESSOR
ZR391055 制造商:ZORAN 制造商全稱:ZORAN 功能描述:Integrated DTV System On a Chip
ZR39140 制造商:ZORAN 制造商全稱:ZORAN 功能描述:INTEGRATED DIGITAL TV PROCESSORS
ZR39150 制造商:ZORAN 制造商全稱:ZORAN 功能描述:INTEGRATED DIGITAL TV PROCESSORS
ZR39151 制造商:ZORAN 制造商全稱:ZORAN 功能描述:INTEGRATED DIGITAL TV PROCESSORS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*