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參數(shù)資料
| 型號(hào)： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 30/66頁 |
| 文件大小： | 441K |
| 代理商： | ZR38650 |
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ZR38650
PROCESSOR GENERAL DESCRIPTION
With its versatile internal architecture, general purpose instruc-
tion set and high speed, the ZR38650’s core processor is also
capable of executing many other types of algorithms for a wide
variety of DSP applications. These algorithms can add differen-
tiating product features to the basic audio decoding functions.
With the ZR38650’s state-of-the-art performance these addition-
al features take little processing time or program memory.
A high level of performance is made possible by the 32-bit wide
instruction set which allows the device to perform a large
number of concurrent operations. For example, in a single
instruction cycle the following operations can be performed:
Fetch two source operands from registers, execute an arith-
metic operation and store the result in a register.
Update two data address pointers
Perform two parallel data move operations
Generate the next program address
Fetch the next program instruction.
Individual bit and immediate data instructions along with the
ZR38650’s four-level zero-overhead loop and repeat instruc-
tions, produce very compact code. Most instructions execute in
a single cycle.
The ZR38650 uses an internal clock rate of up to 100 MHz to
achieve 50-million instructions per second (50-MIPS) perfor-
mance. This allows accessing internal data memory twice per
instruction cycle. An internal programmable phase-locked loop
(PLL) multiplier/divider circuit permits any external crystal or
input clock to be used (in the range of 12-50 MHz).
The ZR38650’s optimized 20-bit (120 dB) data precision make it
particularly well suited for compact disk-quality audio applica-
tions including audio equalization, special effects and audio
mixing where the 16-bit data precision of conventional fixed-
point DSPs is insufficient. Furthermore, by providing high perfor-
mance support for block floating-point operations to extend
dynamic range (including one cycle exponent detection and two
cycle normalization), ZR38650-based systems are inherently
more cost effective to implement than 24-bit precision fixed-
point DSPs which expand dynamic range solely via extended
data precision. High performance block floating-point is due to
the ZR38650’s bi-directional barrel shifter, a feature unavailable
on most conventional 16- and 24-bit fixed-point DSPs.
To ease programming and increase speed, the ZR38650 archi-
tecture provides a general purpose data register file which can
provide up to four source registers and two destination registers
per instruction. A total of eight 20-bit data registers are provided,
with two registers extended to 48-bits for use as accumulator
registers with 8-bit overflow protection.
The ZR38650 also provides a dual address generator and
register file capable of generating two independent addresses
per instruction cycle. The address generator supports modulo
and bit-reversed addressing, in addition to a complete set of pre-
and post-modify addressing modes.
The ZR38650 has many built-in memory resources. A large 2k x
32-bit program/data RAM is available on-chip in additional to the
mask programmable 20k x 32-bit ROM. The already large
internal 10k x 20-bit data RAM along with program/data memory
can be extended on the 32-bit external data bus and 20-bit
memory address bus, with up to 1M words in a unified address
space. Programmable wait-states accommodate lower-cost
slow external memories and byte-wide configurations can be
used for lower chip count if desired.
PROCESSOR FUNCTIONAL DESCRIPTION
Architectural Overview
Figure 12 shows the detailed functional units of the ZR38650
processor. The data path consists of the Arithmetic Unit, the
portions of Memory used for data, and its associated Address
Generation Unit. The control path is the Instruction Unit, the
portions of Memory used for program, and its associated
Program Sequence Unit. The remainder are the Input/Output
Ports and the System Interface.
Data flow between data path units is over the single 20-bit Data
Bus with a corresponding 20-bit Data Address Bus. Control flow
is over the single 32-bit Program Data Bus with a corresponding
20-bit Program Address Bus. These dual data and address
buses are multiplexed to single external buses for external mem-
ories. This simple space-efficient bus structure maintains high
performance as each internal bus makes two transfers per
instruction cycle and each unit is self-contained with its own local
memory.
The high performance of the ZR38650 is apparent from the
power of the data functional units with their attendant instruc-
tions and their being matched by the power of the control
functional units and their instructions. Both are described in turn.
Data and control paths are assured of working together in
parallel because of the fast interconnecting bus structure and
the wide-word instruction set controlling both. This view of the
operation by function and instruction can confirm basic bench-
mark performance. In actual designs, the powerful assembler
and simulator show the details of the pipelined operations and
intermeshing of functions and transfers to assure balanced
operation.
Arithmetic Unit
The arithmetic unit performs all data path operations in the pro-
cessor, using a full-function ALU, a bi-directional barrel shifter
and a 20 x 20-bit multiplier, all operating out of the multiport
register file. The seven ports allow two transfers in or out of the
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