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參數(shù)資料
| 型號(hào)： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 44/66頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ZR38650 |
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44
ZR38650
TYPICAL CONFIGURATIONS
Stand Alone (No Host)
Figure 17 shows a ZR38650 in a typical stand-alone configura-
tion without a host microprocessor but with various optional
external memories. For the lowest cost, only a byte-wide ROM
need be used for loading a developer-written program that
governs the decoder operation. The standard ZR38650 has a
Reset bootstrap loading routine in its internal ROM that reads
the program/data from the external byte-wide ROM at the
address location Hex 40000. The boot-strap recognizes the
external ROM rather than waiting for commands from a host that
does not exist in this configuration.
An alternative is to use the optional 32-bit wide program/data
ROM shown. With the MMAP pin pulled-up, reset execution will
start directly from this external ROM at the address location Hex
8000 and can continue there with the developer-written
program.
The optional program/data RAM can be used in any configura-
tion, including with hosts, for additional 32-bit directly executable
program (with data) memory space. If needed only for data then
this RAM may be only 16 or 24 bits wide.
The compressed data stream is input through the internal
S/PDIF receiver which also acts as a clock master for the output
DACs. This master clock can be selected to be 256 x SR or
384 x SR. The internal clock divider on the ZR38650 generates
the clocking for the three slave DACs that provide the six-
channel audio output.
Note that the PLL capacitor connected to FLTCAP, and the
bypass capacitors on VDDA, should all be mounted close to the
ZR38650 package with short leads over the GNDA analog
ground plane, using normal good design practice for high fre-
quency mixed-signal circuits.
Optical To
TTL S/PDIF
Input
20 pF
20 pF
XTAL
4-40 MHz
XTI
XTO
GND
GNDA
FLTCAP
47 nF
0.1μF
47 μF
Tant.
VDDA
VDD
+3.3V
27
Ω
SPFRX
32
20
CS
RD
32
RESET
INT
System
Reset
System
Interrupt
SCKIN
WSB
SCKB
SDB
SDC
SDD
ZR38650
DAC
DAC
DAC
Left
Right
Left Surround
Right Surround
Center
Subwoofer
Data
L/R
DCLK
CLK
Data
L/R
DCLK
CLK
Data
L/R
DCLK
CLK
f
S
64 f
S
256 f
S
Address
Decode
Byte-Wide Bootstrap ROM
(Optional)
CS
CS
OE
OE
OE
CS
WR
WR
A
A
A
D
A[19:0]
D
D
D[31:0]
Program/Data RAM
(Optional)
Program/Data ROM
(Optional)
8
32
GPIO
6
Figure 17. Typical ZR38650 Stand-Alone Configuration With External Memories
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