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參數(shù)資料
| 型號： | ZR38650 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 35/66頁 |
| 文件大小： | 441K |
| 代理商： | ZR38650 |
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35
ZR38650
The instructions divide into eight classes or bit-pattern formats
summarized in Table 19. It is here that the full power of the
ZR38650 is most evident. The first three classes provide the full
function of the Arithmetic Unit with its operate fields (Opcode
and Operand), but also simultaneous parallel operations. The
parallel operate fields (Parallel Opcode and Parallel Operand)
specify single and double, direct and indirect transfers with the
sources and destinations along with address generation modify
operations. The Bit instructions are also parallel operations. The
last five classes of instructions are for the large-field direct data
transfers and program control.
For classes IV and V the possible source or destination register
is a General Register. For parallel operations, the possible
source and destination registers include the Auxiliary Registers
as well as the General Registers.
Table 19: Instruction Class Summary Table
I. Single operand ALU operations with parallel transfer operations
For parallel transfer operations there are the following six sub-
classes:
with the most powerful being the last which can do the following
four types of sequential dual transfers:
All memory references in this subclass are indirect and with
possible address modification.
Table 18: Instruction Set Summary
Instructions
Arithmetic Unit
Address
Generati
on Unit
Program
Sequence Unit
Arithmetic
Logic
Multiplier
ABS
AND, ANDI
BFY
MOVE
Delayed
Branch
ADD, ADDI
DEC
MADD
Conditional
DB
ASHift, ASHI
INC
MNEG
Jump to SW
Interrupt
CMP, CMPI
LSHift, LSHI
MSUB
LOOP
CMPA
OR, ORI
MUL, MULI
RePeaT
CMPZ
XOR, XORI
MULSU
DIVS
NOP
MULUU
DIVU
CLRBit
MOVEMAX
SETBit
MOVEMIN
TSTBit
NEG
NORM
NORMMAX
SUB
MACROS
CLeaR
POP
DO
PUSH
Jump
Conditional
JuMP
unconditional
Jump
SubRoutine
ReTurn
Interrupt
ReTurn
Subroutine
Class Code
Op-
code
Oper-
and
Parallel Opcode
Parallel Operands
II. Two operand ALU operations with parallel transfer operations
Class
Opcode
Operands
Parallel Opcode
Parallel Operands
III. Three operand ALU operations with parallel transfer operations
Opcode
Operands
Parallel Opcode
Parallel Operands
IV. Load/Store direct
Class Code
Register
Address
V. Load Immediate
Class Code
Register
Data
VI. Conditional delayed branch
Class Code
Condition Code
Address
VII. Repeat immediate
Class Code
Data
VIII. Software jump to interrupt immediate
Class Code
Interrupt #
i
Register-to-register transfers, single
ii
Load register immediate (6-bits), single
iii
Register-to-memory transfers, single
iv
Memory-to-register transfers, single
v
Address modify, single and dual
vi
Single and dual transfers including memory-to-memory
(through a register) and with optional address modify.
First transfer
Second transfer
Data register to memory
Data register to memory
Data register to memory
Memory to data register
Memory to data register
Data register to memory
Memory to data register
Memory to data register
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