參數(shù)資料
型號(hào)： STPC12HEYC
廠商： 意法半導(dǎo)體
英文描述： X86 Core PC Compatible System-on-Chip for Terminals
中文描述： x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù)： 55/111頁(yè)
文件大?。?/td> 1896K
代理商： STPC12HEYC
ELECTRICAL SPECIFICATIONS
Issue 1.0 - July 24, 2002
55/111
10d Memory access to 8-bit ISA Slave
SA[19:0] & SBHE valid before IOR#, IOW# asserted
ISACLK2X to IOW# valid
11a Memory access to 16-bit ISA Slave - 2BCLK
11b Memory access to 16-bit ISA Slave - Standard 3BCLK
11c Memory access to 16-bit ISA Slave - 4BCLK
11d Memory access to 8-bit ISA Slave - 2BCLK
Memory access to 8-bit ISA Slave - Standard 3BCLK
ALE# asserted before ALE# negated
ALE# asserted before MEMR#, MEMW# asserted
13a Memory Access to 16-bit ISA Slave
13b Memory Access to 8-bit ISA Slave
ALE# asserted before SMEMR#, SMEMW# asserted
13c Memory Access to 16-bit ISA Slave
13d Memory Access to 8-bit ISA Slave
ALE# asserted before IOR#, IOW# asserted
ALE# asserted before AL[23:17]
14a Non compressed
14b Compressed
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
15a Memory Access to 16-bit ISA Slave- 4 BCLK
15e Memory Access to 8-bit ISA Slave- Standard Cycle
ALE# negated before LA[23:17] invalid (non compressed)
ALE# negated before LA[23:17] invalid (compressed)
MEMR#, MEMW# asserted before LA[23:17]
22a Memory access to 16-bit ISA Slave.
22b Memory access to 8-bit ISA Slave.
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
23b Memory access to 16-bit ISA Slave Standard cycle
23e Memory access to 8-bit ISA Slave Standard cycle
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
23h Memory access to 16-bit ISA Slave Standard cycle
23l Memory access to 16-bit ISA Slave Standard cycle
IOR#, IOW# asserted before IOR#, IOW# negated
23o Memory access to 16-bit ISA Slave Standard cycle
23r Memory access to 8-bit ISA Slave Standard cycle
MEMR#, MEMW# asserted before SA[19:0]
24b Memory access to 16-bit ISA Slave Standard cycle
24d Memory access to 8-bit ISA Slave - 3BLCK
24e Memory access to 8-bit ISA Slave Standard cycle
24f Memory access to 8-bit ISA Slave - 7BCLK
SMEMR#, SMEMW# asserted before SA[19:0]
24h
Memory access to 16-bit ISA Slave Standard cycle
24i
Memory access to 16-bit ISA Slave - 4BCLK
24k
Memory access to 8-bit ISA Slave - 3BCLK
24l
Memory access to 8-bit ISA Slave Standard cycle
Note: The signal numbering refers to
Table 4-8
2T
2T
Cycle
Cycles
10e
11
2T
2T
2T
2T
2T
1T
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
11e
12
13
2T
2T
Cycles
Cycles
13
2T
2T
2T
Cycles
Cycles
Cycles
13e
14
15T
15T
Cycles
Cycles
15
11T
11T
14T
14T
Cycles
Cycles
Cycles
Cycles
18a
18a
22
13T
13T
Cycles
Cycles
23
9T
9T
Cycles
Cycles
23
9T
9T
Cycles
Cycles
23
9T
9T
Cycles
Cycles
24
10T
10T
10T
10T
Cycles
Cycles
Cycles
Cycles
24
10T
10T
10T
10T
Cycles
Cycles
Cycles
Cycles
Table 4-14. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
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