參數(shù)資料
型號(hào): STPC12HEYC
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù): 25/111頁(yè)
文件大小: 1896K
代理商: STPC12HEYC
PIN DESCRIPTION
Issue 1.0 - July 24, 2002
25/111
MCLK,
Mouse Clock line. Mouse data is latched
by the controller on each negative clock edge
produced on this pin. The mouse can be disabled
by pulling this pin low by software control.
MDATA,
Mouse Data Line. 11-bits of data are
shifted serially through this line when data is being
transferred. Data is synchronised to MCLK.
2.2.15. PARALLEL PORT
PE
Paper End.Input status signal from printer.
SLCT
Printer Select. Printer selected input.
BUSY#
Printer Busy.
Input status signal from printer.
ERR#
Error. Input status signal from printer.
ACK#
Acknowledge.
Input status signal from printer.
PDDIR#
Parallel Device Direction.
Bidirectional control line output.
STROBE#
PCS/Strobe#.
Data transfer strobe line to printer.
INIT#
Initialize Printer.This output sends an
initialize command to the connected printer.
AUTOFD#
Automatic Line feed.This output sends
a command to the connected printer to
automatically generate line feed on received
carriage returns.
SLCTIN#
Select In. Printer select output.
PPD[7-0]
Parallel Port Data Lines Data transfer
lines to printer. Bidirectional depending on modes.
2.2.16. MISCELLANEOUS
SPKRD
Speaker Drive. This is the output to the
speaker and is the AND of the counter 2 output
with bit 1 of Port 61h and drives an external
speaker driver. This output should be connected
to a 7407 type high voltage driver.
SCAN_ENABLE
Reserved This pin is reserved
for Test and Miscellaneous functions. It has to be
set to ‘0’ or connected to ground in normal
operation.
COL_SEL
Colour Select.Can be used for Picture
in Picture function. Note however that this signal,
brought out from the video pipeline, is not in sync
with the VGA output signals, i.e. the VGA signals
run four clock cycles after the Col_Sel signal.
2.2.17. JTAG INTERFACE
TCLK
Test clock
TDI
Test data input
TMS
Test mode input
TDO
Test data output
TRST
Test reset input
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