參數(shù)資料
型號: STPC12HEYC
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 45/111頁
文件大?。?/td> 1896K
代理商: STPC12HEYC
ELECTRICAL SPECIFICATIONS
Issue 1.0 - July 24, 2002
45/111
Note 1: PCI clock at 33MHz
WLC
White Level Current
15.00 mA
18.50 mA
Table 4-4. RAMDAC DC Specification
Symbol
Parameter
Min
Max
Table 4-5. VGA RAMDAC Power Consumption
DCLK
(MHz)
-
6.25 - 135
DAC mode
(State)
Shutdown
Active
P
Max
(mW)
VDD_DAC
= 2.45V
0
150
VDD_DAC
= 2.7V
0
180
Table 4-6. 2.5V Power Consumptions (V
CORE
+ VDD_x_PLL + VDD_DAC)
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
Mode
DCLK
(MHz)
PMU
(State)
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
P
Max
(W)
V
2.5V
=2.45V
1.5
2.5
2.1
2.1
1.9
2.8
2.5
3.3
V
2.5V
=2.7V
1.9
3.0
2.6
3.6
2.4
3.5
3.1
4.1
66
133 (x2)
66
SYNC
Stopped
135
66
133 (x2)
90
ASYNC
Stopped
135
Table 4-7. 3.3V Power Consumptions (V
DD
)
HCLK
(MHz)
CPUCLK
(MHz)
MCLK
(MHz)
DCLK
(MHz)
6.26
135
6.26
135
PMU
(State)
P
Max
(mW)
130
215
150
240
66
133 (x2)
66
Full Speed
66
133 (x2)
90
Full Speed
Table 4-8. PLL Power Consumptions
PLL name
P
Max
(mW)
VDD_PLL
= 2.45V
5
5
5
5
5
5
5
VDD_PLL
= 2.7V
10
10
10
10
10
10
10
VDD_DCLK_PLL
VDD_DEVCLK_PLL
VDD_HCLKI_PLL
VDD_HCLKO_PLL
VDD_MCLKI_PLL
VDD_MCLKO_PLL
VDD_PCICLK_PLL
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