參數(shù)資料
型號: STPC12HEYC
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 54/111頁
文件大小: 1896K
代理商: STPC12HEYC
ELECTRICAL SPECIFICATIONS
54/111
Issue 1.0 - July 24, 2002
4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS
Table 4-8
and
Table 4-14
list the AC characteris-
tics of the ISA interface.
Figure 4-8 ISA Cycle (ref
Table 4-14
)
Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
The clock has not been represented as it is dependent on the ISA Slave mode.
Valid AENx
Valid Address
Valid Address, SBHE*
V.Data
VALID DATA
54
28
26
64
59
58
55
23
61
48
47
57
27
24
42
41
10
11
34
33
3
22
56
29
25
9
18
2
12
38
37
15
14
13
ALE
AEN
LA [23:17]
SA [19:0]
CONTROL (Note 1)
IOCS16#
MCS16#
IOCHRDY
READ DATA
WRITE DATA
Table 4-14. ISA Bus AC Timing
Name
2
3
Parameter
LA[23:17] valid before ALE# negated
LA[23:17] valid before MEMR#, MEMW# asserted
3a Memory access to 16-bit ISA Slave
3b Memory access to 8-bit ISA Slave
SA[19:0] & SBHE valid before ALE# negated
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
10a Memory access to 16-bit ISA Slave
10b Memory access to 8-bit ISA Slave
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
10c Memory access to 16-bit ISA Slave
Note: The signal numbering refers to
Table 4-8
Min
5T
Max
Units
Cycles
5T
5T
1T
Cycles
Cycles
Cycles
9
10
2T
2T
Cycles
Cycles
10
2T
Cycle
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