參數(shù)資料
型號(hào): STPC12HEYC
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù): 50/111頁(yè)
文件大?。?/td> 1896K
代理商: STPC12HEYC
ELECTRICAL SPECIFICATIONS
50/111
Issue 1.0 - July 24, 2002
4.5.3. SDRAM INTERFACE
Figure 4-5
,
Table 4-10
,
Table 4-11
lists the AC
characteristics of the SDRAM interface. The
MCLKx clocks are the input clock of the SDRAM
devices.
The PC100 memory is recommended to reach
90MHz operation.
Figure 4-5. SDRAM Timing Diagram
MCLKI
STPC.output
STPC.input
MCLKx
T
delay
T
setup
T
hold
T
output (min)
T
output (max)
T
cycle
T
high
T
low
Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range
Name
Tcycle
Thigh
Tlow
Parameter
MCLKI Cycle Time
MCLKI High Time
MCLKI Low Time
MCLKI Rising Time
MCLKI Falling Time
MCLKx to MCLKI delay
MCLKI to RAS# Valid
MCLKI to CAS# Valid
MCLKI to CS# Valid
MCLKI to DQM[ ] Outputs Valid
MCLKI to MD[ ] Outputs Valid
MCLKI to MA[ ] Outputs Valid
MCLKI to MWE# Valid
MD[63:0] setup to MCKLI
MD[63:0] hold from MCKLI
Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK not activated
Min
10
4
4
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
Tdelay
2.1
Toutput
1.6
1.6
1.6
1.35
1.35
1.6
1.6
7.5
-0.36
5.2
5.2
5.2
5.2
5.2
5.2
5.2
Tsetup
Thold
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