參數(shù)資料
型號(hào): STPC12HEYC
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 37/111頁
文件大?。?/td> 1896K
代理商: STPC12HEYC
STRAP OPTION
Issue 1.0
- July 24, 2002
37/
111
3.1.3. HCLK PLL STRAP REGISTER
This register is read only.
HCLK_STRAP0
Access = 0022h/0023h
Regoffset =05Fh
7
6
5
4
3
2
1
0
RSV
MD[26]
MD[25]
MD[24]
RSV
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-6
Rsv
These bits are fixed to ‘0’
Bits 5-3
MD[26:24]
These pins reflect the values sampled on MD[26:24] pins respectively
and control the Host clock frequency synthesizer as shown in
Table 3-1
Bits 2-0
Rsv
Reserved
Table 3-1. HCLK Frequency Configuration
MD[3]
0
0
0
0
MD[2]
0
0
0
0
MD[26]
0
0
0
0
All other settings are reserved
MD[25]
0
0
1
1
MD[24]
0
1
0
1
HCLK Speed
25 MHz
50 MHz
60 MHz
66 MHz
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