參數(shù)資料
型號(hào)： STPC12HEYC
廠(chǎng)商： 意法半導(dǎo)體
英文描述： X86 Core PC Compatible System-on-Chip for Terminals
中文描述： x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁(yè)數(shù)： 22/111頁(yè)
文件大小： 1896K
代理商： STPC12HEYC
PIN DESCRIPTION
22/111
Issue 1.0 - July 24, 2002
IRQ_MUX[3:0]
Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are
to be encoded before connection to the STPC
Atlas using ISACLK and ISACLKX2 as the input
selection strobes.
Note that IRQ8B, which by convention is
connected to the RTC, is inverted before being
sent to the interrupt controller, so that it may be
connected directly to the IRQ# pin of the RTC.
ISAOE#
Bidirectional OE Control. This signal
controls the OE signal of the external transceiver
that connects the IDE DD bus and ISA SA bus.
KBCS#
Keyboard Chip Select.This signal is
asserted if a keyboard access is decoded during a
I/O cycle.
ZWS#
Zero Wait State. This signal, when
asserted by addressed device, indicates that
current cycle can be shortened.
DACK_ENC[2:0]
DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Atlas before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
DREQ_MUX[1:0]
ISA Bus Multiplexed DMA
Request. These are the ISA bus DMA request
signals. They are to be encoded before
connection to the STPC Atlas using ISACLK and
ISACLKX2 as the input selection strobes.
TC
ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
2.2.5. PCMCIA INTERFACE
RESET
Card Reset.This output forces a hard
reset to a PC Card.
A[25:0]
Address Bus. These are the 25 low bits of
the system address bus of the PCMCIA bus.
These pins are used as an input when an PCMCIA
bus owns the bus and are outputs at all other
times.
D[15:0]
I/O Data Bus (PCMCIA). These are the
external PCMCIA databus pins.
IORD#
I/O Read. This output is used with REG# to
gate I/O read data from the PC Card, (only when
REG# is asserted).
IOWR#
I/O Write This output is used with REG#
to gate I/O write data from the PC Card, (only
when REG# is asserted).
WP
Write Protect. This input indicates the status
of the Write Protect switch (if fitted) on memory PC
Cards (asserted when the switch is set to write
protect).
BVD1, BVD2
Battery Voltage Detect. These
inputs will be generated by memory PC Cards that
include batteries and are an indication of the
condition of the batteries. BVD1 and BVD2 are
kept asserted high when the battery is in good
condition.
READY#/BUSY#/IREQ#
request.This input is driven low by memory PC
Cards to signal that their circuits are busy
processing a previous write command.
Ready/busy/Interrupt
WAIT#
Bus Cycle Wait.This input is driven by the
PC Card to delay completion of the memory or I/O
cycle in progress.
OE#
Output Enable. OE# is an active low output
which is driven to the PC Card to gate Memory
Read data from memory PC Cards.
WE#/PRGM#
Write Enable. This output is used by
the host for gating Memory Write data. WE# is
also used for memory PC Cards that have
programmable memory.
REG#
Attribute Memory Select.This output is
inactive (high) for all normal accesses to the Main
Memory of the PC Card. I/O PC Cards will only
respond to IORD# or IOWR# when REG# is active
(low). Also see
Section 2.2.7.
CD1#, CD2#
Card Detect. These inputs provide
for the detection of correct card insertion. CD#1
and CD#2 are positioned at opposite ends of the
connector to assist in the detection process.
These inputs are internally grounded on the PC
Card therefore they will be forced low whenever a
card is inserted in a socket.
CE1#, CE2#
Card Enable. These are active low
output signals provided from the PCIC. CE#1
enables even Bytes, CE#2 odd Bytes.
ENABLE#
Enable. This output is used to activate/
select a PC Card socket. ENABLE# controls the
external address buffer logic.C card has been
detected (CD#1 and CD#2 = '0').
ENIF#
ENIF. This output is used to activate/select
a PC Card socket.
EXT_DIR
EXternal Transceiver Direction Control.
This output is high during a read and low during a
write. The default power up condition is write
(low). Used for both Low and High Bytes of the
Data Bus.
VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0,
VPP2_EN1
Power Control. Five output signals
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