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參數(shù)資料
| 型號： | STPC12HEYC |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | X86 Core PC Compatible System-on-Chip for Terminals |
| 中文描述： | x86內(nèi)核PC兼容系統(tǒng)上的終端芯片 |
| 文件頁數(shù)： | 107/111頁 |
| 文件大小： | 1896K |
| 代理商： | STPC12HEYC |
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DESIGN GUIDELINES
Issue 1.0 - July 24, 2002
107/111
3
SYSRSTI#
(Power Good)
Measure SYSRSTI# of STPC
See
Figure 4-3
for waveforms.
Verify reset generation circuit:
- device reference
- components value
5
HCLK
Measure HCLK is at selected frequency
25MHz < HCLK < 66MHz
HCLK wire must be as short as possible
6
PCI clocks
Measure PCICLKO:
- maximum is 33MHz by standard
- check it is at selected frequency
- it is generated from HCLK by a division
(1/2, 1/3 or 1/4)
Check PCICLKI equals PCICLKO
Verify PCICLKO loops to PCICLKI.
Verify maximum skew between any PCI clock
branch is below 2ns.
In Synchronous mode, check MCLKI.
7
Memory
clocks
Measure MCLKO:
- use a low-capacitance probe
- maximum is 90MHz
- check it is at selected frequency
- In SYNC mode MCLK=HCLK
- in ASYNC mode, default is 66MHz
Check MCLKI equals MCLKO
Verify load on MCLKI.
Verify MCLK programming (BIOS setting).
4
SYSRSTO#
Measure SYSRSTO# of STPC
See
Figure 4-3
for waveforms.
Verify SYSRSTI# duration.
Verify SYSRSTI# has no glitch
Verify clocks are running.
8a
PCI cycles
Check PCI signals are toggling:
- FRAME#, IRDY#, TRDY#, DEVSEL#
- these signals are active low.
Check, with a logic analyzer, that first
PCI cycles are the expected ones:
memory read starting at address with
lower bits to 0xFFF0
Verify PCI slots
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
9a
ISA
cycles
to
boot memory
Check RMRTCCS# & MEMRD#
Check directly on boot memory pin
Verify MEMCS16#:
- must not be asserted for 8-bit memory
Verify IOCHRDY is not be asserted
Verify ISAOE# pin:
- it controls IDE / ISA bus demultiplexing
8b
Local Bus
cycles
to
boot memory
Check FCS0# & PRD#
Check directly on boot memory pin
Verify HCLK speed and CPU clock mode.
9b
Check, with a logic analyzer, that first
Local Bus cycles are the expected one:
memory read starting at the top of boot
memory less 16 bytes
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
10
The CPU fills its first cache line by fetching 16 bytes from boot memory.
Then, first instructions are executed from the CPU.
Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU
=> Minimum hardware is correctly set, CPU executes code.
Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.
Check:
How
Troubleshooting
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STPCATLAS | X86 Core PC Compatible System-on-Chip for Terminals |
| STPC12HDYC | X86 Core PC Compatible System-on-Chip for Terminals |
| STPC12HDYI | X86 Core PC Compatible System-on-Chip for Terminals |
| STPCD0166BTA3 | PC Compatible Embedded Microprocessor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STPC12HEYI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core PC Compatible System-on-Chip for Terminals |
| STPC1MBBL | 制造商:Panduit Corp 功能描述: |
| STPC1MBGR | 制造商:Panduit Corp 功能描述:Cable Assembly STP 1m 26AWG Modular Plug to Modular Plug PL-PL |
| STPC3MBBL | 制造商:Panduit Corp 功能描述: |
| STPC3MBGR | 制造商:Panduit Corp 功能描述:Cable Assembly STP 3m 26AWG Modular Plug to Modular Plug PL-PL |
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