參數(shù)資料
型號: STPC12HEYC
廠商: 意法半導(dǎo)體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內(nèi)核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 27/111頁
文件大?。?/td> 1896K
代理商: STPC12HEYC
PIN DESCRIPTION
Issue 1.0 - July 24, 2002
27/111
Table 2-5. Signal value on Reset
Signal Name
SYSRSTI# active
SYSRSTI# inactive
SYSRSTO# active
release of SYSRSTO#
BASIC CLOCKS AND RESETS
XTALO
ISA_CLK
ISA_CLK2X
OSC14M
DEV_CLK
HCLK
PCI_CLKO
DCLK
MEMORY CONTROLLER
MCLKO
CS#[3:1]
CS#[0]
MA[10:0], BA[0]
RAS#[1:0], CAS#[1:0]
MWE#, DQM[7:0]
MD[63:0]
PCI INTERFACE
AD[31:0]
CBE[3:0], PAR
FRAME#, TRDY#, IRDY#
STOP#, DEVSEL#
PERR#, SERR#
PCI_GNT#[2:0]
ISA BUS INTERFACE
ISAOE#
RMRTCCS#
LA[23:17]
SA[19:0]
SD[15:0]
BHE#, MEMR#
MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown
REF#
ALE, AEN
DACK_ENC[2:0]
TC
GPIOCS#
RTCDS#, RTCRW#, KBCS#
RTCAS
PCMCIA INTERFACE
RESET
A[23:0]
D[15:0]
IORD#, IOWR#, OE#
WE#, REG#
CE2#, CE1#, VCC5_EN, VCC3_EN
VPP_PGM, VPP_VCC
LOCAL BUS INTERFACE
PA[24:0]
PD[15:0]
PRD#
PBE#[1:0], FCS0#, FCS_0H#
14MHz
Low
14MHz
14MHz
24MHz
Oscillating at the speed defined by the strap options.
HCLK divided by 2 or 3, depending on the strap options.
17MHz
7MHz
66MHz if asynchonous mode, HCLK speed if synchronized mode.
High
High
0x00
High
High
Input
SDRAM init sequence:
Write Cycles
0x0000
Low
Input
Input
Input
High
First prefetch cycles
when not in Local Bus mode.
High
Hi-Z
Unknown
0xFFFXX
Unknown
Unknown
Low
First prefetch cycles
when in ISA or PCMCIA mode.
Address start is 0xFFFFF0
0x00
0xFFF03
0xFF
High
High
High
Unknown
Low
Input
Input
Hi-Z
Hi-Z
Unknown
0x04
Low
High
Low
Unknown
Unknown
Unknown
Unknown
High
High
Low
High
0x00
0xFF
High
First prefetch cycles
using RMRTCCS#
Unknown
Unknown
Unknown
High
First prefetch cycles
0xFF
High
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