
PIN DESCRIPTION
Issue 1.0 - July 24, 2002
15/111
ISA BUS INTERFACE
LA[23:17]
SA[19:0]
SD[15:0]
IOCHRDY
ALE
BHE#
MEMR#, MEMW#
SMEMR#, SMEMW#
IOR#, IOW#
MASTER#
MCS16#
IOCS16#
REF#
AEN
IOCHCK#
RTCRW#
RTCDS#
RTCAS
RMRTCCS#
GPIOCS#
IRQ_MUX[3:0]
DACK_ENC[2:0]
DREQ_MUX[1:0]
TC
ISAOE#
KBCS#
ZWS#
O BD8STRUP_FT
O BD8STRUP_FT
I/O BD8STRP_FT
I
BD8STRUP_FT
O BD4STRP_FT
O BD8STRUP_FT
I/O BD8STRUP_FT
O BD8STRP_FT
I/O BD8STRUP_FT
I
BD4STRUP_FT
I
BD4STRUP_FT
I
BD4STRUP_FT
I
BD8STRP_FT
O BD8STRUP_FT
I
BD4STRUP_FT
O BD4STRP_FT
O BD4STRP_FT
O BD4STRP_FT
O BD4STRP_FT
I/O BD4STRP_FT
I
BD4STRP_FT
O BD4STRP_FT
I
BD4STRP_FT
O BD4STRP_FT
I
BD4STRP_FT
I/O BD4STRP_FT
I BD4STRP_FT
Unlatched Address Bus
Latched Address Bus
Data Bus
I/O Channel Ready
Address Latch Enable
System Bus High Enable
Memory Read & Write
System Memory Read and Write
I/O Read and Write
Add On Card Owns Bus
Memory Chip Select 16
I/O Chip Select 16
Refresh Cycle
Address Enable
I/O Channel Check (ISA)
RTC Read / Write#
RTC Data Strobe
RTC Address Strobe
ROM / RTC Chip Select
General Purpose Chip Select
Multiplexed Interrupt Request
DMA Acknowledge
Multiplexed DMA Request
ISA Terminal Count
ISA (0) / IDE (1) SELECTION
External Keyboard CHIP SELECT
ZERO WAIT STATE
7
20
16
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
4
3
2
1
1
1
1
PCMCIA INTERFACE
RESET
A[23:0]
D[15:0]
IORD#, IOWR#
O BD8STRP_FT
O BD8STRUP_FT
I/O BD8STRP_FT
O BD8STRUP_FT
Reset
Address Bus
Data Bus
I/O Read and Write
DMA Request // Write Protect
I/O Size is 16 bit
Battery Voltage Detect
Busy / Ready# // Interrupt Request
Wait
Output Enable // DMA Terminal Count
Write Enable // DMA Terminal Count
DMA Acknowledge // Register
Card Detect
Card Enable
Power Switch control: 5 V power
Power Switch control: 3.3 V power
Power Switch control: Program power
Power Switch control: VCC power
General Purpose Input
1
24
16
2
WP / IOIS16#
I
BD4STRUP_FT
1
BVD2, BVD1
READY# / IREQ#
WAIT#
OE#
WE#
REG#
CD2#, CD1#
CE2#, CE1#
VCC5_EN
VCC3_EN
VPP_PGM
VPP_VCC
GPI#
I
I
I
BD4STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
O BD8STRUP_FT
O BD4STRP_FT
O BD4STRUP_FT
I
BD4STRUP_FT
O BD4STRP_FT
O BD4STRP_FT
O BD8STRP_FT
O BD8STRP_FT
O BD4STRP_FT
I
BD4STRP_FT
2
1
1
1
1
1
2
2
1
1
1
1
1
Table 2-2. Definition of Signal Pins
Signal Name
Dir
Buffer Type
1
Description
Qty
Note
1
; See
Table 2-3
for buffer type descriptions