參數(shù)資料
型號: MC916X1CTH16B1
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝: QFP-120
文件頁數(shù): 69/172頁
文件大?。?/td> 1200K
代理商: MC916X1CTH16B1
MOTOROLA
MC68HC916X1
160
MC68HC916X1TS/D
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external
sources are at valid VOH/VOL prior to SCK transitioning between valid VOL and VOH. Due to process variation,
logic decision point voltages of the data and clock signals can differ, which can corrupt data if slower transition
times are used.
Table 81 QSPI Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H 200 pF load on all QSPI pins)
1
Num
Function
Symbol
Min
Max
Unit
0
Operating Frequency
Master
Slave
fop
DC
1/4
System Clock Frequency
1
Cycle Time
Master
Slave
tqcyc
4
510
tcyc
2
Enable Lead Time
Master
Slave
tlead
2
128
tcyc
3
Enable Lag Time
Master
Slave
tlag
2
1/2
SCK
tcyc
4
Clock (SCK) High or Low Time
Master
Slave2
tsw
2 tcyc – 60
2 tcyc – n
255 tcyc
ns
5
Sequential Transfer Delay
Master
Slave (Does Not Require Deselect)
ttd
17
13
8192
tcyc
6
Data Setup Time (Inputs)
Master
Slave
tsu
30
20
ns
7
Data Hold Time (Inputs)
Master
Slave
thi
0
20
ns
8
Slave Access Time
ta
—1
tcyc
9
Slave MISO Disable Time
tdis
—2
tcyc
10
Data Valid (after SCK Edge)
Master
Slave
tv
50
ns
11
Data Hold Time (Outputs)
Master
Slave
tho
0
ns
12
Rise Time
Input
Output
tri
tro
2
30
s
ns
13
Fall Time
Input3
Output
tfi
tfo
2
30
s
ns
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I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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.
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