
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
93
6.5 GPT Registers
The following section provides a summary of GPT registers and their contents.
The GPTMCR contains parameters for configuring the GPT.
STOP — Stop Clocks
0 = Internal clocks not shut down
1 = Internal clocks shut down
FRZ1 — Not Implemented
FRZ0 — FREEZE Assertion Response
0 = Ignore IMB FREEZE Signal
1 = FREEZE the current state of the GPT
STOPP — Stop Prescaler
0 = Normal operation
1 = Stop prescaler and pulse accumulator from incrementing. Ignore changes to input pins.
INCP — Increment Prescaler
0 = Has no meaning
1 = If STOPP is asserted, increment prescaler once and clock input synchronizers once.
SUPV — Supervisor/Unrestricted Data Space
This bit has no effect because the CPU16 always operates in the supervisor mode.
IARB[3:0] — Interrupt Arbitration Identification
The value in this field is used to arbitrate between simultaneous interrupt service requests of the same
priority. Each module that can generate interrupts has an IARB field. In order to implement an arbitration
scheme, each IARB field must be set to a different non-zero value. If an interrupt request from a module
that has an IARB field value of $0 is recognized, the CPU16 processes a spurious interrupt exception.
The reset value of all IARB fields other than that of the SCIM is $0 (no priority), to preclude interrupt
processing during reset.
GPTMTR — GPT Module Test Register
$YFF902
This address is reserved for GPT factory test.
IPA[3:0] — Interrupt Priority Adjust
This field specifies which GPT interrupt source is given highest internal priority. Refer to Table 45.
GPTMCR — GPT Module Configuration Register
$YFF900
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP
FRZ1 FRZ0 STOPP INCP
0
SUPV
0
IARB[3:0]
RESET:
0
1
0
ICR — GPT Interrupt Configuration Register
$YFF904
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IPA[3:0]
0
IPL[2:0]
IVBA[3:0]
0
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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