參數(shù)資料
型號： MC916X1CTH16B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 105/172頁
文件大?。?/td> 1200K
代理商： MC916X1CTH16B1
MOTOROLA
MC68HC916X1
38
MC68HC916X1TS/D
If a chip select function is given the same address as a microcontroller module or memory array, an
access to that address goes to the module or array, and the chip select signal is not asserted.
Each chip-select pin has two or more functions. Configuration out of reset is determined by operat-
ing mode. In single-chip mode, all chip select pins except CS10 and CS0 are configured for alter-
nate functions or discrete output. In expanded modes, appropriate pins are configured for chip
select operation, but chip select signals cannot be asserted until a transfer size is chosen. In fully
expanded mode, data bus pins can be held low to enable alternate chip-select pin functions.
Table 21 shows allocation of chip selects and discrete outputs to MCU pins.
3.9.1 Chip Select Registers
Pin assignment registers (CSPAR) determine functions of chip select pins. Pin assignment regis-
ters also determine port size (8- or 16-bit) for dynamic bus allocation.
A pin data register (PORTC) latches discrete output data.
Blocks of addresses are assigned to each chip select function. Block sizes of 2 Kbytes to 1 Mbyte
can be selected by writing values to the appropriate base address register (CSBAR). However, be-
cause the logic state of ADDR20 is always the same as the state of ADDR19, the largest usable
block size is 512 Kbytes. Address blocks for separate chip-select functions can overlap, however,
they must have the same number of wait states if they do.
Chip-select option registers (CSOR) determine timing of and conditions for assertion of chip-select
signals. Eight parameters, including operating mode, access size, synchronization, and wait state
insertion can be specified.
3.9.2 Pin Assignment Registers
The pin assignment registers contain pairs of bits that determine the functions of chip-select pins.
Table 22 shows pin assignment field encoding. Pin functions are shown in Tables 23 and 24 fol-
lowing the register diagrams.
Reset state of the pin assignment registers depends on operating mode. In the register diagrams,
reset values are shown in the following order: single-chip mode, 8-bit expanded mode, and 16-bit
expanded mode. The notation DATA# indicates that a bit goes to the logic level of that data bus pin
on reset. Data bus lines have weak pull-ups. During reset in 16-bit expanded mode, an active ex-
ternal device can pull the data lines low to select alternate functions.
Table 21 Chip Select Pin Allocation
Chip Select Function
Alternate Function
Discrete Outputs Function
CS0
BR
—
CSM
BG
—
CSE
BGACK
—
CS3
FC0
PC0
—
FC1
PC1
CS5
FC2
PC2
CS6
ADDR19
PC3
CS10
ADDR23
ECLK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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