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MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
99
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps, or PCLK, to be PWMCNT input. Refer to Table 51.
SFA/B — PWMA/B Slow/Fast Select
0 = PWMA/B period is 256 PWMCNT increments long.
1 = PWMA/B period is 32768 PWMCNT increments long.
Table 52 shows the effects of settings on PWM frequency for a 16.78-MHz system clock.
F1A/B — Force Logic Level One on PWMA/B
0 = Force logic level zero output on PWMA/B pin
1 = Force logic level one output on PWMA/B pin
PWMA/PWMB — PWM Duty Cycle Registers A/B
$YFF926, $YFF927
These registers are associated with the pulse-width value of the PWM output on the corresponding
PWM pin. A value of $00 loaded into one of these registers results in a continuously low output on
the corresponding pin. A value of $80 results in a 50% duty cycle output. Maximum value ($FF) se-
lects an output that is high for 255/256 of the period.
PWMCNT — PWM Count Register
$YFF928
PWMCNT is the 16-bit free-running counter associated with the PWM functions of the GPT module.
PWMBUFA/B — PWM Buffer Registers A/B
$YFF92A, $YFF92B
These read-only registers contain values associated with the duty cycles of the corresponding
PWM. Reset state for both registers is $00.
PRESCL — GPT Prescaler
$YFF92C
The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as ze-
ros. Reset state is $0000.
Table 51 PWM Prescaler/PCLK Select Taps
PPR[2:0]
System Clock
Divide-By Factor
000
2
001
4
010
8
011
16
100
32
101
64
110
128
111
PCLK
Table 52 Effects of SFA/B Settings on PWM Frequency
PPR[2:0]
Prescaler Tap
SFA/B = 0
SFA/B = 1
000
Div 2 = 8.39 MHz
32.8 kHz
256 Hz
001
Div 4 = 4.19 MHz
16.4 kHz
128 Hz
010
Div 8 = 2.10 MHz
8.19 kHz
64.0 Hz
011
Div 16 = 1.05 MHz
4.09 kHz
32.0 Hz
100
Div 32 = 524 kHz
2.05 kHz
16.0 Hz
101
Div 64 = 262 kHz
1.02 kHz
8.0 Hz
110
Div 128 = 131 kHz
512 Hz
4.0 Hz
111
PCLK
PCLK/256
PCLK/32768
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Freescale Semiconductor, Inc.
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