參數(shù)資料
型號(hào)： MC916X1CTH16B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 10/172頁
文件大?。?/td> 1200K
代理商： MC916X1CTH16B1
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
107
7.4.2 QSPI Registers
The programmer's model for the QSPI submodule consists of the QSM global and pin control reg-
isters, four QSPI control registers, one status register, and the 80-byte QSPI RAM.
The CPU can read and write to registers and RAM. The four control registers must be initialized
before the QSPI is enabled to ensure defined operation. SPCR1 should be written last because it
contains QSPI enable bit SPE. Asserting this bit starts the QSPI. The QSPI control registers are
reset to a defined state and can then be changed by the CPU. Reset values are shown below each
register.
Table 58 shows a memory map of the QSPI.
Writing a different value into any control register except SPCR2 while the QSPI is enabled disrupts
operation. SPCR2 is buffered to prevent disruption of the current serial transfer. After completion of
the current serial transfer, the new SPCR2 values become effective.
Writing the same value into any control register except SPCR2 while the QSPI is enabled has no
effect on QSPI operation. Rewriting NEWQP[3:0] in SPCR2 causes execution to restart at the des-
ignated location.
Table 57 QSPI Pins
Pin Name(s)
Mnemonic(s)
Mode
Function
Master In Slave Out
MISO
Master
Slave
Serial Data Input to QSPI
Serial Data Output from QSPI
Master Out Slave In
MOSI
Master
Slave
Serial Data Output from QSPI
Serial Data Input to QSPI
Serial Clock
SCK
Master
Slave
Clock Output from QSPI
Clock Input to QSPI
Peripheral Chip Selects
PCS[3:1]
Master
Select Peripherals
Peripheral Chip Select
Slave Select
PCS0
SS
Master
Slave
Selects Peripheral
Causes mode fault
Initiates Serial Transfer
Table 58 QSPI Memory Map
Address
Name
Usage
$YFFC18
SPCR0
QSPI Control Register 0
$YFFC1A
SPCR1
QSPI Control Register 1
$YFFC1C
SPCR2
QSPI Control Register 2
$YFFC1E
SPCR3
QSPI Control Register 3
$YFFC1F
SPSR
QSPI Status Register
$YFFD00
RR[0:F]
QSPI Receive Data (16 Words)
$YFFD20
TR[0:F]
QSPI Transmit Data (16 Words)
$YFFD40
CR[0:F]
QSPI Command Control (8 Words)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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