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參數(shù)資料
| 型號(hào)： | MC916X1CTH16B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 5/172頁(yè) |
| 文件大?。?/td> | 1200K |
| 代理商： | MC916X1CTH16B1 |
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MOTOROLA
MC68HC916X1
102
MC68HC916X1TS/D
7.3 QSM Registers
QSM registers are divided into four categories: QSM global registers, QSM pin control registers,
QSPI submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined
in separate sections below. Writes to unimplemented register bits have no meaning or effect, and
reads from unimplemented bits always return a logic zero value.
7.3.1 Global Registers
The QSM global registers contain system parameters used by both the QSPI and the SCI submod-
ules. These registers contain the bits and fields used to configure the QSM.
The QSMCR contains parameters for the QSM/CPU/intermodule bus (IMB) interface.
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
STOP places the QSM in a low-power state by disabling the system clock in most parts of the module.
The QSMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is
not readable. However, writes to RAM or any register are guaranteed to be valid while STOP is assert-
ed. STOP can be negated by the CPU and by reset.
The system software must stop each submodule before asserting STOP to avoid complications at re-
start and to avoid data corruption. The SCI submodule receiver and transmitter should be disabled, and
the operation should be verified for completion before asserting STOP. The QSPI submodule should be
stopped by asserting the HALT bit in SPCR3 and by asserting STOP after the HALTA flag is set.
FRZ1 — FREEZE Assertion Response
0 = Ignore the FREEZE signal on the IMB
1 = Halt the QSPI (on a transfer boundary)
FRZ1 determines what action is taken by the QSPI when the FREEZE signal of the IMB is asserted.
FREEZE is asserted whenever the CPU enters the background mode.
FRZ0 — Not Implemented
Bits [12:8] — Not Implemented
SUPV — Supervisor/Unrestricted Data Space
This bit has no effect because the CPU16 always operates in the supervisor mode.
IARB[3:0] — Interrupt Arbitration Identification Number
The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each
module that can generate interrupt requests must be assigned a unique, non-zero IARB field value.
QTEST — QSM Test Register
$YFFC02
QTEST is used during factory testing of the QSM.
QSMCR — QSM Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP FRZ1 FRZ0
0
SUPV
0
IARB[3:0]
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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