
MOTOROLA
MC68HC916X1
44
MC68HC916X1TS/D
This field only affects the response of chip selects and does not affect interrupt recognition by the CPU.
AVEC — Autovector Enable
0 = External interrupt vector enabled
1 = Autovector enabled
This field selects one of two methods of acquiring the interrupt vector during the interrupt acknowledge
cycle. It is not usually used with a chip select pin.
If the chip select is configured to trigger on an interrupt acknowledge cycle (SPACE[1:0] = %00) and the
AVEC field is set to one, the chip select automatically generates an AVEC in response to the interrupt
acknowledge cycle. Otherwise, the vector must be supplied by the requesting device.
3.9.5 Port C Data Register
Bit values in port C determine the state of chip-select pins used for discrete output. When a pin is
assigned as a discrete output, the value in this register appears at the output. This is a read/write
register. Bit 7 is not used. Writing to this bit has no effect, and it always returns zero when read.
3.9.6 Chip Select Reset Operation
The reset values of the chip select pin assignment fields in CSPAR0 and CSPAR1 depend on the
for more information.
The BYTE[1:0] field in option register CSORBT has a reset value of both bytes, but CSOR[10:0]
have a reset value of disable, as they should not select external devices until an initial program sets
up the base and option registers.
1. “All” means that a chip select signal is asserted regardless of the priority
of the interrupt.
Table 30 Interrupt Priority Level Field Encoding
IPL[2:0]
SPACE[1:0] = 00
SPACE[1:0] = 01, 10, 11
000
All1
Data or Program
001
IPL1
Data
010
IPL2
Program
011
IPL3
Reserved
100
IPL4
Reserved
101
IPL5
Data
110
IPL6
Program
111
IPL7
Reserved
PORTC — Port C Data Register
$YFFA41
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
0
RESERVED
PC3
PC2
PC1
PC0
RESET:
0
1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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