參數(shù)資料
型號： MC916X1CTH16B1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120
封裝： QFP-120
文件頁數(shù)： 117/172頁
文件大小： 1200K
代理商： MC916X1CTH16B1
MC68HC916X1
MOTOROLA
MC68HC916X1TS/D
49
When the corresponding pin is configured for edge detection, a PORTFE bit is set if an edge is de-
tected. PORTFE bits remain set, regardless of the subsequent state of the corresponding pin, until
cleared. To clear a bit, first read PORTFE, then write the bit to zero. When a pin is configured for
general-purpose I/O or for use as an interrupt request input, PORTFE bits do not change state.
This register determines which vector in the exception vector table is used for interrupts generated
by the port F edge-detect logic. Program PFIVR[7:0] to the value pointing to the appropriate inter-
rupt vector. Refer to 4 Central Processing Unit for interrupt vector assignments.
PFLVR determines the priority level of the port F edge-detect interrupt. The reset value is $00, in-
dicating that the interrupt is disabled. When several sources of interrupts from the SCIM are arbi-
trating for the same level, the port F edge-detect interrupt has the lowest arbitration priority.
3.10.4 Port G
Port G is available in single-chip mode only. These pins are always configured for use as general-
purpose I/O in single-chip mode.
3.10.5 Port H
Port H is available in single-chip and 8-bit expanded modes only. The function of these pins is de-
termined by the operating mode. There is no pin assignment register associated with this port.
These port data registers can be read or written any time the MCU is not in emulation mode. Reset
has no effect.
PORTFE — Port F Edge-Detect Flag Register
$YFFA2B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PEF7 PEF6
RESERVED
PEF0
RESET:
0
PFIVR — Port F Edge-Detect Interrupt Vector Register
$YFFA2B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
PFIVR[7:0]
RESET:
0
PFLVR — Port F Edge-Detect Interrupt Level Register
$YFFA2D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
0
PFLV[2:0]
RESET:
0
PORTG — Port G Data Register
$YFFA0C
PORTH — Port H Data Register
$YFFA0D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
RESET:
U
F
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e
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S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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