
MOTOROLA
MC68HC916X1
94
MC68HC916X1TS/D
IPL[2:0] — Interrupt Priority Level
This field specifies the priority level of interrupts generated by the GPT.
IVBA[3:0] — Interrupt Vector Base Address
Most significant nibble of interrupt vector numbers generated by the GPT. Refer to Table 45.
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and
PORTGP holds the 8-bit data.
DDRGP[7:0] — Port GP Data Direction Register
0 = Input only
1 = Output
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines
which pins are affected. OC1D determines what the outputs are.
OC1M[5:1] — OC1 Mask Field
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] — OC1 Data Field
0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1 match.
1 = If OC1 mask bit is set, set the corresponding output compare pin on OC1 match.
OC1D[5:1] correspond to OC[5:1].
Table 45 GPT Interrupt Sources
Name
Source Number
Source
Vector Number
—
0000
Adjusted Channel
IVBA : 0000
IC1
0001
Input Capture 1
IVBA : 0001
IC2
0010
Input Capture 2
IVBA : 0010
IC3
0011
Input Capture 3
IVBA : 0011
OC1
0100
Output Compare 1
IVBA : 0100
OC2
0101
Output Compare 2
IVBA : 0101
OC3
0110
Output Compare 3
IVBA : 0110
OC4
0111
Output Compare 4
IVBA : 0111
IC4/OC5
1000
Input Capture 4/Output Compare 5
IVBA : 1000
TO
1001
Timer Overflow
IVBA : 1001
PAOV
1010
Pulse Accumulator Overflow
IVBA : 1010
PAI
1011
Pulse Accumulator Input
IVBA : 1011
DDRGP/PORTGP — Port GP Data Direction Register/Port GP Data Register
$YFF906
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRGP
PORTGP
RESET:
0
OC1M/OC1D — OC1 Action Mask Register/OC1 Action Data Register
$YFF908
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OC1M[5:1]
0
OC1D[5:1]
0
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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