
MOTOROLA
MC68HC916X1
122
MC68HC916X1TS/D
8.4 SRAM Operation
There are five SRAM operating modes. They include the following:
1.
The RAM module is in normal mode when powered by VDD. The array can be accessed by
byte, word, or long word. A byte or aligned word (high-order byte is at an even address)
access only takes one bus cycle or two system clocks. A long word or misaligned word ac-
cess requires two bus cycles.
2.
Standby mode is intended to preserve RAM contents when VDD is removed. SRAM con-
tents are maintained by a power source connected to the VSTBY pin. The standby voltage
is referred to as VSB. Circuitry within the SRAM module switches to the higher of VDD or
VSB with no loss of data. When SRAM is powered from the VSTBY pin, access to the array
is not guaranteed. If standby operation is not desired, connect the VSTBY pin to VSS.
3.
Reset mode allows the CPU to complete the current bus cycle before resetting. When a
synchronous reset occurs while a byte or word SRAM access is in progress, the access is
completed. If reset occurs during the first word access of a long-word operation, only the
first word access is completed. If reset occurs during the second word access of a long
word operation, the entire access is completed. Data being read from or written to the RAM
may be corrupted by asynchronous reset.
4.
Test mode is used for factory testing of the RAM array.
5.
Writing the STOP bit of RAMMCR causes the SRAM module to enter stop mode. The RAM
array is disabled which, if necessary, allows external logic to decode SRAM addresses but
all data is retained. If VDD falls below VSB, internal circuitry switches to VSB, as in standby
mode. Exit the stop mode by clearing the STOP bit.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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